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Cc:     gregkh@linuxfoundation.org, mturquette@baylibre.com,
        robh+dt@kernel.org, mark.rutland@arm.com,
        shubhrajyoti.datta@gmail.com, devicetree@vger.kernel.org,
        soren.brinkmann@xilinx.com,
        Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
To:     devel@driverdev.osuosl.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, shubhrajyoti.datta@gmail.com
Subject: Re: [PATCH v3 07/10] clk: clock-wizard: Update the fixed factor divisors
From:   Stephen Boyd <sboyd@kernel.org>
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Date:   Sun, 05 Jan 2020 12:00:13 -0800
Message-Id: <20200105200014.4904320678@mail.kernel.org>
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Quoting shubhrajyoti.datta@gmail.com (2019-11-27 22:36:14)
> From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
>=20
> Update the fixed factor clock registration to register the divisors.
>=20
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
> ---
>  drivers/clk/clk-xlnx-clock-wizard.c | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
>=20
> diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-c=
lock-wizard.c
> index 4c6155b..75ea745 100644
> --- a/drivers/clk/clk-xlnx-clock-wizard.c
> +++ b/drivers/clk/clk-xlnx-clock-wizard.c
> @@ -491,9 +491,11 @@ static int clk_wzrd_probe(struct platform_device *pd=
ev)
>         u32 reg, reg_f, mult;
>         unsigned long rate;
>         const char *clk_name;
> +       void __iomem *ctrl_reg;
>         struct clk_wzrd *clk_wzrd;
>         struct resource *mem;
>         int outputs;
> +       unsigned long flags =3D 0;
>         struct device_node *np =3D pdev->dev.of_node;
> =20
>         clk_wzrd =3D devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERN=
EL);
> @@ -564,19 +566,22 @@ static int clk_wzrd_probe(struct platform_device *p=
dev)
>                 goto err_disable_clk;
>         }
> =20
> -       /* register div */
> -       reg =3D (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) &
> -                       WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SH=
IFT;
> +       outputs =3D of_property_count_strings(np, "clock-output-names");
> +       if (outputs =3D=3D 1)
> +               flags =3D CLK_SET_RATE_PARENT;

What does the number of clk outputs have to do with the ability to
change the rate of a parent clk? The commit text doesn't inform me of
what this is for either. Please help us understand.

>         clk_name =3D kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->=
dev));
>         if (!clk_name) {
>                 ret =3D -ENOMEM;
>                 goto err_rm_int_clk;
>         }
> =20