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Date: Mon, 15 Oct 2001 19:16:16 +0200
From: Manfred Spraul <manfred@colorfullife.com>
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To: "Eric W. Biederman" <ebiederm@xmission.com>
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Subject: Re: SMP processor rework help needed
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> For intel the initial determination is made having the cpus race on
> the apic bus.  The cpu that sends a message first gets the lowest
> apicid.  Though I need to see how the P4 Xeon does it, as the apic
> bus is actually unused.

Huh?

24547202.pdf: (i.e. volume 3 of the ia32 SDM)
<<<<<<<<
The APIC ID register is loaded at power up by sampling configuration
data that is driven onto pins of the processor. For the Pentium 4 and P6
family processors, pins A11# and A12# and pins BR0# through BR3# are
sampled; for the Pentium processor, pins BE0# through BE3# are sampled.
<<<<<<

--
	Manfred
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