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Message-ID: <d8cddd005901e64133e9ecbb14ec8fdf3269972d.camel@buserror.net>
From:   Scott Wood <oss@buserror.net>
To:     yingjie_bai@126.com, Kumar Gala <galak@kernel.crashing.org>
Cc:     Bai Yingjie <byj.tea@gmail.com>,
        Benjamin Herrenschmidt <benh@kernel.crashing.org>,
        Paul Mackerras <paulus@samba.org>,
        Michael Ellerman <mpe@ellerman.id.au>,
        Christophe Leroy <christophe.leroy@c-s.fr>,
        "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>,
        Jason Yan <yanaijie@huawei.com>,
        Diana Craciun <diana.craciun@nxp.com>,
        Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
        Nicholas Piggin <npiggin@gmail.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Allison Randal <allison@lohutok.net>,
        linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
Date:   Mon, 06 Jan 2020 12:05:59 -0600
In-Reply-To: <20200106042957.26494-2-yingjie_bai@126.com>
References: <20200106042957.26494-1-yingjie_bai@126.com>
         <20200106042957.26494-2-yingjie_bai@126.com>
Organization: Red Hat
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Subject: Re: [PATCH v3 2/2] powerpc/mpc85xx: also write addr_h to spin table
 for 64bit boot entry
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On Mon, 2020-01-06 at 12:29 +0800, yingjie_bai@126.com wrote:
> From: Bai Yingjie <byj.tea@gmail.com>
> 
> CPU like P4080 has 36bit physical address, its DDR physical
> start address can be configured above 4G by LAW registers.
> 
> For such systems in which their physical memory start address was
> configured higher than 4G, we need also to write addr_h into the spin
> table of the target secondary CPU, so that addr_h and addr_l together
> represent a 64bit physical address.
> Otherwise the secondary core can not get correct entry to start from.
> 
> Signed-off-by: Bai Yingjie <byj.tea@gmail.com>
> ---
>  arch/powerpc/platforms/85xx/smp.c | 9 +++++++++
>  1 file changed, 9 insertions(+)

Acked-by: Scott Wood <oss@buserror.net>

-Scott