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From:   Yash Shah <yash.shah@sifive.com>
To:     Anup Patel <anup@brainfault.org>
CC:     Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        "Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Bin Meng <bmeng.cn@gmail.com>,
        Green Wan <green.wan@sifive.com>,
        Allison Randal <allison@lohutok.net>,
        Alexios Zavras <alexios.zavras@intel.com>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        "bp@suse.de" <bp@suse.de>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        Sachin Ghadi <sachin.ghadi@sifive.com>
Subject: RE: [PATCH v2 2/2] riscv: cacheinfo: Add support to determine no. of
 L2 cache way enabled
Thread-Topic: [PATCH v2 2/2] riscv: cacheinfo: Add support to determine no. of
 L2 cache way enabled
Thread-Index: AQHVwew4Uxrz+iLoAkGC7gaBkWkw+qfdXmOAgAE5Y/A=
Date:   Tue, 7 Jan 2020 03:55:49 +0000
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