Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp330080ybl; Tue, 7 Jan 2020 20:26:32 -0800 (PST) X-Google-Smtp-Source: APXvYqwoG5YhO32nckqMMJSyTNk3jOOjw19vl6KrH28ZkmbuI5EhEIlpYIehPGguuB4MA8ZLGEqt X-Received: by 2002:a9d:6758:: with SMTP id w24mr2858874otm.155.1578457592505; Tue, 07 Jan 2020 20:26:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578457592; cv=none; d=google.com; s=arc-20160816; b=yfVDZQUa4nbRX2DhwczsHThhTgSVItGxtcItrwzzovaA8jQT2bDsfrTyPrlqIn/GOf aHXHvByMIH5CPUUdtmWzKf9qESD7w6eOaE7AV8U8aBbmqGO1jQJvYmEZgBc7nme9RuWV MQlLxyyFHxoIK6Vwa60EJptRKyI/A9x56TP7jwjyNW6IFxK/9ZZxyAwfdnS9qKV/De/M pGawAt4GRN9iG5NxTkuff0AtdUB5WEUNxAnhjlKGkkz4TDKPOdOCmjW/gkitLvOXo0LO 49nXW/PHvl2jrVkx/LnejLwlDiDgDA8WhM/3zA/TCCZLKyEITZJyMU1CHRYTNB/b+DDt e0tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=Z3ACX3vP5nNFEx8B7eX+Er9D7XJtGr/zcelaygn+3Bo=; b=04A7Y2ccrOBYC10aos+gFJO5snawWjze7K/aqxbUCHsO/gVjzfYH+XmPL3ZTxfGo2+ O7cRqqyTnqSbpinZfzNTnD0hMn48RBQ4hXKz1c+uJQ4T3tGkQPsZAuSw9lmqkI+qTCVo 2xT38zHEmesDi5hIQEF2U8uy/8cBe4m2JlbjPlXK3Hpiww9p9625KgVYv17v7DOSMtid JmdQFVetsEYMzqkFmnAPUN5VJg9ylzLBtov1KnQ791s7+ifSSqujsoCyWuLYvODAyxQT FZdrTGfsQfEIoZ16djx0unxTz+KMoYXnLS7KNWUR864wumBcw4rgIHFwHO4GmCzRKndm +K9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=K4BXBSu9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h18si1107526otj.114.2020.01.07.20.26.20; Tue, 07 Jan 2020 20:26:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=K4BXBSu9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727099AbgAHEZf (ORCPT + 99 others); Tue, 7 Jan 2020 23:25:35 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:10398 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbgAHEZc (ORCPT ); Tue, 7 Jan 2020 23:25:32 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 07 Jan 2020 20:25:14 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 07 Jan 2020 20:25:32 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 07 Jan 2020 20:25:32 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan 2020 04:25:31 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 8 Jan 2020 04:25:31 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 07 Jan 2020 20:25:31 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v7 07/21] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings Date: Tue, 7 Jan 2020 20:25:01 -0800 Message-ID: <1578457515-3477-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578457514; bh=Z3ACX3vP5nNFEx8B7eX+Er9D7XJtGr/zcelaygn+3Bo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=K4BXBSu9MScA2PYYrIYzqBATVzLgxunoGmK6jTRnjrTgpmuZfc8ct269dqAvCJwlf +OsRAuc+g66pmrnhp1uJ2In5pMFTYE4bYoMkwPr9WQKkXRZa3hEwVRV89rA6ztyis1 b/FH5fQtCgOqoRFO8MQeTMg7BDZ3/t12Hx+dYtSrDEB+icTWneOmkgQknfiQOtfnPz 2OwpSRTdvBM7Zjbrxsts81R5J0t+dzflZ3cMJBI+7DoETYyVz/zRDAYqGIssroFqPC 4R+q4qMMfUTcAkcAkEYzkK3b+dgz6VGvxpFRvfPJkVJeinwAm+DZoazu7O0FQ3KEvj +FINrRFDdSiAw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra PMC has 3 clocks clk_out_1, clk_out_2, and clk_out_3. This patch documents PMC clock bindings and adds a header defining Tegra PMC clock ids. Tested-by: Dmitry Osipenko Reviewed-by: Dmitry Osipenko Reviewed-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 12 ++++++++++++ include/dt-bindings/soc/tegra-pmc.h | 15 +++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/dt-bindings/soc/tegra-pmc.h diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml index 3ff34b348141..5b5c42a00264 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -40,6 +40,15 @@ properties: Must contain an entry for each entry in clock-names. See ../clocks/clocks-bindings.txt for details. + '#clock-cells': + const: 1 + description: + Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. + Consumer of PMC clock should specify the desired clock by having + the clock ID in its "clocks" phandle cell with pmc clock provider. + See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC + clock IDs. + '#interrupt-cells': const: 2 description: @@ -296,6 +305,7 @@ required: - reg - clock-names - clocks + - '#clock-cells' dependencies: "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] @@ -307,12 +317,14 @@ examples: #include #include + #include tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; nvidia,invert-interrupt; nvidia,suspend-mode = <0>; diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h new file mode 100644 index 000000000000..f7c866404456 --- /dev/null +++ b/include/dt-bindings/soc/tegra-pmc.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H +#define _DT_BINDINGS_SOC_TEGRA_PMC_H + +#define TEGRA_PMC_CLK_OUT_1 0 +#define TEGRA_PMC_CLK_OUT_2 1 +#define TEGRA_PMC_CLK_OUT_3 2 + +#define TEGRA_PMC_CLK_MAX 3 + +#endif /* _DT_BINDINGS_SOC_TEGRA_PMC_H */ -- 2.7.4