Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp330324ybl;
        Tue, 7 Jan 2020 20:26:56 -0800 (PST)
X-Google-Smtp-Source: APXvYqxhdvQx97mLKusKbL7dTPgRz18+QywR8DnlmIY6Tj70kioj/vxMKliuW7KqC67fXAqtiXOY
X-Received: by 2002:a05:6830:1188:: with SMTP id u8mr2769313otq.274.1578457616689;
        Tue, 07 Jan 2020 20:26:56 -0800 (PST)
ARC-Seal: i=1; a=rsa-sha256; t=1578457616; cv=none;
        d=google.com; s=arc-20160816;
        b=oKNJ65DDEvVz4w06bwAWFNEA4IRbsbE5uNwT4bkAb+cQTJXJdmZwL6u7Zk6RRZmGml
         C2l9/HR1G/p4JlMf4inRJJDwLuI3SiNTmP6CIcntp69W1kQFJZZqYSSxVlzUYjYQn9xs
         wd3n99mlA5yDQxyVar08e62at5WUh/CcEGDwqFCOb4ruJVIpq0Uxkmjiz5QBlD2AG2CU
         hfmp140Elx4humRywJsqq63uJ+wfgDqKjVbUCokPVxaIrmgl0R9eKoFOBWkixCYSyj0b
         UIjli1RrvLLuQIpPwv90tbd8JzzSe615KlGgMomvM2QgGpFPK4ZOe6UCXUuiyUpqg1Ln
         GxbQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:dkim-signature:mime-version:references
         :in-reply-to:message-id:date:subject:cc:to:from;
        bh=gkcJtn8jnkfrlt7lseMCLMoUPqIVSBgfxdajsl9lga0=;
        b=aTkjEumczoxnisz6GzbdPO0Vbtdci+LWzBq5RXbuIkiIZLV3oVlLC/nlcQAqxZC68C
         EakTT2doD1QktyraO7EQ0iuhJ8HLigALmKGCr4Ce+OxcAP3gqvcrcQaf6+0FxbvFpwKC
         IPdz73upEOLzwnSgPA7QSkrzlLNrr9PPpctkxcU5+sa4CjnMh3DF5YNGHbd4oHtRjrCJ
         XHa/gZ4CVzUyqVwzgQySSWBc8SGG7aUpVgpV+XGYr+ic2ymAorx/rCoHu4TrV2enlQZW
         LRNCvPCfDdkDqDrv08xigZYqQYY7cy0wmXqPJoSb2KgoZoBlw6FKMu0PIyJfyh4mqNvt
         ivdQ==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=XKz7IFlI;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id n203si1142950oia.112.2020.01.07.20.26.45;
        Tue, 07 Jan 2020 20:26:56 -0800 (PST)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=XKz7IFlI;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1727259AbgAHEZw (ORCPT <rfc822;yuvraaj@gmail.com> + 99 others);
        Tue, 7 Jan 2020 23:25:52 -0500
Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:10338 "EHLO
        hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1727239AbgAHEZu (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Tue, 7 Jan 2020 23:25:50 -0500
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5e15599d0000>; Tue, 07 Jan 2020 20:25:01 -0800
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Tue, 07 Jan 2020 20:25:50 -0800
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Tue, 07 Jan 2020 20:25:50 -0800
Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com
 (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan
 2020 04:25:49 +0000
Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com
 (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend
 Transport; Wed, 8 Jan 2020 04:25:49 +0000
Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5e1559cb0000>; Tue, 07 Jan 2020 20:25:48 -0800
From:   Sowjanya Komatineni <skomatineni@nvidia.com>
To:     <skomatineni@nvidia.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>, <broonie@kernel.org>,
        <lgirdwood@gmail.com>, <perex@perex.cz>, <tiwai@suse.com>,
        <digetx@gmail.com>, <mperttunen@nvidia.com>,
        <gregkh@linuxfoundation.org>, <sboyd@kernel.org>,
        <robh+dt@kernel.org>, <mark.rutland@arm.com>
CC:     <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
        <spujar@nvidia.com>, <josephl@nvidia.com>,
        <daniel.lezcano@linaro.org>, <mmaddireddy@nvidia.com>,
        <markz@nvidia.com>, <devicetree@vger.kernel.org>,
        <linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
Subject: [PATCH v7 18/21] arm64: tegra: Add clock-cells property to Tegra PMC node
Date:   Tue, 7 Jan 2020 20:25:12 -0800
Message-ID: <1578457515-3477-19-git-send-email-skomatineni@nvidia.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com>
References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1578457501; bh=gkcJtn8jnkfrlt7lseMCLMoUPqIVSBgfxdajsl9lga0=;
        h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
         In-Reply-To:References:X-NVConfidentiality:MIME-Version:
         Content-Type;
        b=XKz7IFlIsDGQi9ot4LNla9E9F1vGheBUVWgHSc4vGynokj2+9xNBWeT6t8uIPJDo3
         igux7YAsiHaYRnAiDdOOEImMEYNN8tWse9TGcyf/fnkGXsV23dmBs7/Q+Y1dd7p+Lk
         pmviUOG3KNs8PRoxl+qwzFCb4IIST5i2kdyJgOCpW5grgIwiCjTTkVpooHN6Ng18bw
         0nENrJyUJWfTh8ifrWhupFtEgq8t0aUiU/jlFQ8o82z/T8tLK59qkBVeRYmi3zNav2
         OwCsABdPpHxkXMRVJfvhl3my5ivHNUhvzxZuirdku8vBMVvFVhTv1+W63CwbrjDJ51
         xnKmE20afJk6A==
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Tegra132 and Tegra210 PMC block has clk_out_1, clk_out_2, clk_out_3,
and a blink clock as a part of PMC.

These clocks are moved from clock driver to pmc driver with pmc as a
clock provider.

Clock ids for these clocks are defined in pmc dt-bindings.

This patch updated device tree to include pmc dt-binding and adds
#clock-cells property with one clock specifier to pmc node.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++-
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 631a7f77c386..79b1e3b01096 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
 	compatible = "nvidia,tegra132", "nvidia,tegra124";
@@ -577,11 +578,12 @@
 		clock-names = "rtc";
 	};
 
-	pmc@7000e400 {
+	tegra_pmc: pmc@7000e400 {
 		compatible = "nvidia,tegra124-pmc";
 		reg = <0x0 0x7000e400 0x0 0x400>;
 		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 	};
 
 	fuse@7000f800 {
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 48c63256ba7f..3e73b76249f9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/reset/tegra210-car.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
 
 / {
 	compatible = "nvidia,tegra210";
@@ -770,16 +771,17 @@
 		compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
 		reg = <0x0 0x7000e000 0x0 0x100>;
 		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&pmc>;
+		interrupt-parent = <&tegra_pmc>;
 		clocks = <&tegra_car TEGRA210_CLK_RTC>;
 		clock-names = "rtc";
 	};
 
-	pmc: pmc@7000e400 {
+	tegra_pmc: pmc@7000e400 {
 		compatible = "nvidia,tegra210-pmc";
 		reg = <0x0 0x7000e400 0x0 0x400>;
 		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
 		clock-names = "pclk", "clk32k_in";
+		#clock-cells = <1>;
 		#interrupt-cells = <2>;
 		interrupt-controller;
 
-- 
2.7.4