Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp331383ybl;
        Tue, 7 Jan 2020 20:28:51 -0800 (PST)
X-Google-Smtp-Source: APXvYqzSzQI4GXImpv+c67BKg4LcZahs+0yIY/rFeT3abnUUQgK2AGArp6CwWjvqPVG0ozCLCtBS
X-Received: by 2002:aca:b984:: with SMTP id j126mr1635625oif.174.1578457731512;
        Tue, 07 Jan 2020 20:28:51 -0800 (PST)
ARC-Seal: i=1; a=rsa-sha256; t=1578457731; cv=none;
        d=google.com; s=arc-20160816;
        b=OqsW8T3OLhtFUoXIqMSnwhep6ixQm5V+VotyJFnMr4EPRHPYULAH3YHmNi2S2RSCDD
         jUW48OjWUW/kqs38csCsPo0PZBQj6P44prVpwAtgPbybmftNF6BCdS+mBNyW4qgDmKnp
         qnQmBOEopOX/pl0AOTVRvP+xSzvrY5jbdwhXYkEz4BJERy2Wb2ViWdHAKEVZH7NSxtGo
         dsa9wAWsIkKhoWhsdkQhBXtbff2iuj8/qXnplVljIF/W5IVvWCADtveKiSU+FHgR9MwX
         5cZOJBgjcbGxgZJgNqryepZ1MWZKmBWtbWbNELNhQJLNUtYqXB5m94BKtOKhNPg3qT8i
         lqDA==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:dkim-signature:mime-version:references
         :in-reply-to:message-id:date:subject:cc:to:from;
        bh=Qd4MoYeB4S9zIPag2VqM/EpPRBCVtbjyGvx0y3gnKVw=;
        b=pz/1q11v/RXA4FskOrwaQY6b21vWL/mTfagrCZD1Q3GgZqVXGf2iSr/byodlXIZjlQ
         8pPsLQ+8/SPIMeRWJeiRDVVFEZh7kxQTJsmfhe8lkBLXGw9NTn/iaUGt6iY+vHHsedhJ
         6O8Wqg2ypItLXczTly/iGkvtTrIeRnAuWY27vptPcDDDv5nNa5C0dAe2r0KV4xj6AS3a
         s9ls4cucDM9x0ek7K2SNTHsqb3pNyuCBAnBmWbK9OYl9Vtkvzao6U2o88wd/2FSp0+k8
         EAhzJyYd1dJKyQcWpb3eLuLAWt1aIwRa2/7zVlqlypdeCk+RngdzOPNeAc/XRBw2guKm
         mrPA==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=YYTeu7BJ;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id m4si1166726otr.122.2020.01.07.20.28.39;
        Tue, 07 Jan 2020 20:28:51 -0800 (PST)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=YYTeu7BJ;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1727400AbgAHE0q (ORCPT <rfc822;yuvraaj@gmail.com> + 99 others);
        Tue, 7 Jan 2020 23:26:46 -0500
Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:10371 "EHLO
        hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1726945AbgAHEZ3 (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Tue, 7 Jan 2020 23:25:29 -0500
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5e1559a70000>; Tue, 07 Jan 2020 20:25:11 -0800
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Tue, 07 Jan 2020 20:25:28 -0800
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Tue, 07 Jan 2020 20:25:28 -0800
Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com
 (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 8 Jan
 2020 04:25:28 +0000
Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com
 (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend
 Transport; Wed, 8 Jan 2020 04:25:28 +0000
Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.162.131]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5e1559b60001>; Tue, 07 Jan 2020 20:25:27 -0800
From:   Sowjanya Komatineni <skomatineni@nvidia.com>
To:     <skomatineni@nvidia.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>, <broonie@kernel.org>,
        <lgirdwood@gmail.com>, <perex@perex.cz>, <tiwai@suse.com>,
        <digetx@gmail.com>, <mperttunen@nvidia.com>,
        <gregkh@linuxfoundation.org>, <sboyd@kernel.org>,
        <robh+dt@kernel.org>, <mark.rutland@arm.com>
CC:     <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
        <spujar@nvidia.com>, <josephl@nvidia.com>,
        <daniel.lezcano@linaro.org>, <mmaddireddy@nvidia.com>,
        <markz@nvidia.com>, <devicetree@vger.kernel.org>,
        <linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
Subject: [PATCH v7 05/21] clk: tegra: Fix Tegra PMC clock out parents
Date:   Tue, 7 Jan 2020 20:24:59 -0800
Message-ID: <1578457515-3477-6-git-send-email-skomatineni@nvidia.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com>
References: <1578457515-3477-1-git-send-email-skomatineni@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1578457511; bh=Qd4MoYeB4S9zIPag2VqM/EpPRBCVtbjyGvx0y3gnKVw=;
        h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
         In-Reply-To:References:X-NVConfidentiality:MIME-Version:
         Content-Type;
        b=YYTeu7BJWni2bHRKqcIY41pSBQqZ6kmABO+wEYlu98yRwNHwYAtXaSEWAc4qEdXwl
         pKLvpzuajpKEGeUXzedGKC8SPymCTXxI9OJafwge0A45lX6+Eqj3iaECtmiEc3FEtG
         Uo4oOXuCpCC4jgsuoZH5YkfnqzZfryG7kFcv2dOBZHLR8o4B+3TAN/YsCBM9/J0/yn
         B5Qnu3JAiqSa04iQ5pWFVu/vZd6N4lTvpUgM40CoPCJ2jhHol9DYkMQJ7p+ocVEtN5
         evtvzPMs5+WI7gDK3VaeKgcb1stVUnve7iFv0rU0LnbOc2qu2CDwEhtLFg4OLCuIZf
         wNeFWckn2d4aA==
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Tegra PMC clock out parents are osc, osc_div2, osc_div4 and extern
clock.

Clock driver is using incorrect parents clk_m, clk_m_div2, clk_m_div4
for PMC clocks.

This patch fixes this.

Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/clk/tegra/clk-tegra-pmc.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
index bec3e008335f..5e044ba1ae36 100644
--- a/drivers/clk/tegra/clk-tegra-pmc.c
+++ b/drivers/clk/tegra/clk-tegra-pmc.c
@@ -49,16 +49,16 @@ struct pmc_clk_init_data {
 
 static DEFINE_SPINLOCK(clk_out_lock);
 
-static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
-	"clk_m_div4", "extern1",
+static const char *clk_out1_parents[] = { "osc", "osc_div2",
+	"osc_div4", "extern1",
 };
 
-static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
-	"clk_m_div4", "extern2",
+static const char *clk_out2_parents[] = { "osc", "osc_div2",
+	"osc_div4", "extern2",
 };
 
-static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
-	"clk_m_div4", "extern3",
+static const char *clk_out3_parents[] = { "osc", "osc_div2",
+	"osc_div4", "extern3",
 };
 
 static struct pmc_clk_init_data pmc_clks[] = {
-- 
2.7.4