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[209.132.180.67]) by mx.google.com with ESMTP id c12si1265676otn.90.2020.01.07.21.25.53; Tue, 07 Jan 2020 21:26:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=NkVCUiKN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726486AbgAHFYC (ORCPT + 99 others); Wed, 8 Jan 2020 00:24:02 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:35493 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726439AbgAHFYB (ORCPT ); Wed, 8 Jan 2020 00:24:01 -0500 Received: by mail-pg1-f195.google.com with SMTP id l24so986628pgk.2 for ; Tue, 07 Jan 2020 21:24:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lllmZMa5R6OSarsk8DAetZxTWweyF2murgh0XlHq6j4=; b=NkVCUiKNiOJ9C+pbhXp0aEB19RPqRC6wDm+6NS8Rr/QZs/IAYhTqfvM5dahItDjNi2 w99fCIjhyz4QnH/H+A5Tkx79ELP7lzPKVSYKJ2AU6rLW3U7TWhWa7Q85F56l0LaPbz78 JJ7+bjD2dnlIc3L6d2ILkOPzx292Vi6xrOtKo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lllmZMa5R6OSarsk8DAetZxTWweyF2murgh0XlHq6j4=; b=tzgU2nO9wt7TN77V3PvmJqX3FGfG8hiy81dP3B16Q5Uuf0dzrG2J8lSKLXtDRx/aeX aWylUKTxA850Vg809mWu8GztxZEi+ysjarF2Yi7DAGtXeVZJo2HA6HMCaYH6va1vlIoo bwAPm85xApqJxJpAToKUuJm3F6PwFS33/2VU7PSFILo/crEj/aKVY11/GxxhCPRMvkZ5 D2n/fHxCtUsTevct3Uf7wd1T+Sa5uYjwx4Uxf8R9h9esDvVpqQbb6tgpVVBQNoN3ksms toI1326KJ6JNP6IQhj1G4/iWNgWQWuZqV0P7S+HkUDts4rq+VW2OK2aFeL1LvyfYQcLn 08zA== X-Gm-Message-State: APjAAAUKFMPHYA8GbS61SEd3HRQfiEG04QL1+o5baXYzh5gO77eLsdg/ 9AFW9ADSV6h1tRJEg8fOzKToXFdIPLU= X-Received: by 2002:a63:d041:: with SMTP id s1mr3417134pgi.363.1578461041186; Tue, 07 Jan 2020 21:24:01 -0800 (PST) Received: from drinkcat2.tpe.corp.google.com ([2401:fa00:1:b:d8b7:33af:adcb:b648]) by smtp.gmail.com with ESMTPSA id n24sm387505pff.12.2020.01.07.21.23.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jan 2020 21:24:00 -0800 (PST) From: Nicolas Boichat To: Rob Herring Cc: David Airlie , Daniel Vetter , Mark Rutland , Matthias Brugger , Tomeu Vizoso , Steven Price , Alyssa Rosenzweig , Liam Girdwood , Mark Brown , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, hsinyi@chromium.org Subject: [PATCH v2 2/7] arm64: dts: mt8183: Add node for the Mali GPU Date: Wed, 8 Jan 2020 13:23:32 +0800 Message-Id: <20200108052337.65916-3-drinkcat@chromium.org> X-Mailer: git-send-email 2.24.1.735.g03f4e72817-goog In-Reply-To: <20200108052337.65916-1-drinkcat@chromium.org> References: <20200108052337.65916-1-drinkcat@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a basic GPU node for mt8183. Signed-off-by: Nicolas Boichat --- Upstreaming what matches existing bindings from our Chromium OS tree: https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/arch/arm64/boot/dts/mediatek/mt8183.dtsi#1348 The evb part of this change depends on this patch to add PMIC dtsi: https://patchwork.kernel.org/patch/10928161/ The binding we use with out-of-tree Mali drivers includes more clocks, this is used for devfreq: the out-of-tree driver switches clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then switches clk_mux back to clk_main_parent: (see https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#423) clocks = <&topckgen CLK_TOP_MFGPLL_CK>, <&topckgen CLK_TOP_MUX_MFG>, <&clk26m>, <&mfgcfg CLK_MFG_BG3D>; clock-names = "clk_main_parent", "clk_mux", "clk_sub_parent", "subsys_mfg_cg"; v2: - Use sram instead of mali_sram as SRAM supply name. - Rename mali@ to gpu@. arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 ++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 104 ++++++++++++++++++++ 2 files changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 1fb195c683c3d01..7d609e0cd9b4975 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "mt8183.dtsi" +#include "mt6358.dtsi" / { model = "MediaTek MT8183 evaluation board"; @@ -30,6 +31,12 @@ &auxadc { status = "okay"; }; +&gpu { + supply-names = "mali", "sram"; + mali-supply = <&mt6358_vgpu_reg>; + sram-supply = <&mt6358_vsram_gpu_reg>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c_pins_0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1ade9153e5c265b..4da3f1ed1c15bf3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -597,6 +597,110 @@ mfgcfg: syscon@13000000 { #clock-cells = <1>; }; + gpu: gpu@13040000 { + compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; + reg = <0 0x13040000 0 0x4000>; + interrupts = + , + , + ; + interrupt-names = "job", "mmu", "gpu"; + + clocks = <&topckgen CLK_TOP_MFGPLL_CK>; + + power-domains = + <&scpsys MT8183_POWER_DOMAIN_MFG_CORE0>, + <&scpsys MT8183_POWER_DOMAIN_MFG_CORE1>, + <&scpsys MT8183_POWER_DOMAIN_MFG_2D>; + + operating-points-v2 = <&gpu_opp_table>; + }; + + gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <625000>, <850000>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + opp-microvolt = <631250>, <850000>; + }; + + opp-340000000 { + opp-hz = /bits/ 64 <340000000>; + opp-microvolt = <637500>, <850000>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + opp-microvolt = <643750>, <850000>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + opp-microvolt = <650000>, <850000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <656250>, <850000>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <662500>, <850000>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + opp-microvolt = <675000>, <850000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <687500>, <850000>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <700000>, <850000>; + }; + + opp-580000000 { + opp-hz = /bits/ 64 <580000000>; + opp-microvolt = <712500>, <850000>; + }; + + opp-620000000 { + opp-hz = /bits/ 64 <620000000>; + opp-microvolt = <725000>, <850000>; + }; + + opp-653000000 { + opp-hz = /bits/ 64 <653000000>; + opp-microvolt = <743750>, <850000>; + }; + + opp-698000000 { + opp-hz = /bits/ 64 <698000000>; + opp-microvolt = <768750>, <868750>; + }; + + opp-743000000 { + opp-hz = /bits/ 64 <743000000>; + opp-microvolt = <793750>, <893750>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <825000>, <925000>; + }; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8183-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; -- 2.24.1.735.g03f4e72817-goog