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Date:   Thu, 09 Jan 2020 16:27:16 +0530
From:   sthella@codeaurora.org
To:     Rob Herring <robh@kernel.org>
Cc:     agross@kernel.org, srinivas.kandagatla@linaro.org,
        mark.rutland@arm.com, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: nvmem: add binding for QTI SPMI SDAM
In-Reply-To: <20200108163943.GA26863@bogus>
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 <20200108163943.GA26863@bogus>
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On 2020-01-08 22:09, Rob Herring wrote:
> On Tue, Dec 24, 2019 at 11:02:12AM +0530, Shyam Kumar Thella wrote:
>> QTI SDAM allows PMIC peripherals to access the shared memory that is
>> available on QTI PMICs. Add documentation for it.
>> 
>> Signed-off-by: Shyam Kumar Thella <sthella@codeaurora.org>
>> ---
>>  .../devicetree/bindings/nvmem/qcom,spmi-sdam.yaml  | 79 
>> ++++++++++++++++++++++
>>  1 file changed, 79 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml
>> 
>> diff --git 
>> a/Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml 
>> b/Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml
>> new file mode 100644
>> index 0000000..8961a99
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml
>> @@ -0,0 +1,79 @@
>> +# SPDX-License-Identifier: GPL-2.0
> 
> Dual license new bindings:
> 
> (GPL-2.0-only OR BSD-2-Clause)
> 
> Please spread the word in QCom.
Sure. I will add Dual license in next patchset.
> 
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/nvmem/qcom,spmi-sdam.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Technologies, Inc. SPMI SDAM DT bindings
>> +
>> +maintainers:
>> +  - Shyam Kumar Thella <sthella@codeaurora.org>
>> +
>> +description: |
>> +  The SDAM provides scratch register space for the PMIC clients. This
>> +  memory can be used by software to store information or communicate
>> +  to/from the PBUS.
>> +
>> +allOf:
>> +  - $ref: "nvmem.yaml#"
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - qcom,spmi-sdam
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  "#address-cells":
>> +    const: 1
>> +
>> +  "#size-cells":
>> +    const: 1
> 
> ranges? The child addresses should be translateable I assume.
The addresses are not memory mapped on the CPU's address domain. They 
are the SPMI addresses which can be accessed over SPMI controller.
> 
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +
>> +patternProperties:
>> +  "^.*@[0-9a-f]+$":
>> +    type: object
>> +
>> +    properties:
>> +      reg:
>> +        maxItems: 1
>> +        description:
>> +          Offset and size in bytes within the storage device.
>> +
>> +      bits:
> 
> Needs a type reference.
Yes. I will add a reference in the next patch set.
> 
>> +        maxItems: 1
>> +        items:
>> +          items:
>> +            - minimum: 0
>> +              maximum: 7
>> +              description:
>> +                Offset in bit within the address range specified by 
>> reg.
>> +            - minimum: 1
> 
> max is 7?
I don't think it is limited to 7 as it is the size within the address 
range specified by reg. If the address range is more than a byte size 
can be more.
> 
>> +              description:
>> +                Size in bit within the address range specified by 
>> reg.
>> +
>> +    required:
>> +      - reg
>> +
>> +    additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +      sdam_1: nvram@b000 {
>> +         #address-cells = <1>;
>> +         #size-cells = <1>;
>> +         compatible = "qcom,spmi-sdam";
>> +          reg = <0xb000 0x100>;
>> +
>> +          /* Data cells */
>> +          restart_reason: restart@50 {
>> +              reg = <0x50 0x1>;
>> +              bits = <7 2>;
> 
> How do you have bit 8 in a 1 byte register?
You are right. Thanks for it. I will correct the example in next patch 
set.
> 
>> +          };
>> +      };
>> +...
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>> Forum,
>>  a Linux Foundation Collaborative Project
>>