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[178.255.168.35]) by smtp.gmail.com with ESMTPSA id s8sm7846492wrt.57.2020.01.09.05.39.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Jan 2020 05:39:27 -0800 (PST) From: Michal Simek To: linux-arm-kernel@lists.infradead.org Cc: Anurag Kumar Vulisha , Jan Kiszka , Mark Rutland , Rajan Vaja , Rob Herring , Ulf Hansson , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] arm64: zynqmp: Setup default number of chipselects for zcu100 Date: Thu, 9 Jan 2020 14:39:15 +0100 Message-Id: <0565b9a88830f0d995d666a9c4bf346641a2b040.1578577147.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is only one chipselect on each connector. Define it directly in board dts file. There should be an option to use more chipselects via gpios. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 2b3757dd74cc..a109e82982ae 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -250,11 +250,13 @@ wlcore: wifi@2 { &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; + num-cs = <1>; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; + num-cs = <1>; }; &uart0 { -- 2.24.0