Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp2215869ybl; Thu, 9 Jan 2020 08:48:36 -0800 (PST) X-Google-Smtp-Source: APXvYqz4ysS5dTieMtDp/BixEuqyGAgBPSFJH0lsaNIMxypcFlB5Thx47QIiuDTVdZIFrf6SwljL X-Received: by 2002:a9d:5888:: with SMTP id x8mr8797636otg.361.1578588510073; Thu, 09 Jan 2020 08:48:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578588510; cv=none; d=google.com; s=arc-20160816; b=ZvkvExcz0ePECAt6AeA8qGIrapmOq5KFm4He+lSk+osT+rMZxMDWQlsJirgGeOntOV uMgBHbyXlNg2tyKoMKY85oRd8bQpW5V1uhCLK/UvxrdbyhCYnF9Lk71nr/QZ53wvHPr+ 2EQQWBJCZI6cjQGjqojOZuOzZH+AvTJuclZGsyDAaJmUkxoECMIf6h2PtTDWetLVd81B m+lSouTfHtLNMtv2iPtqq8i1vPiSfyiLStLxgNzuqpFv4jR9YsFBwpb0Yt4EmWPuoMi7 qJGQzghR7ov/phIt1tkdsPjlc0jOLzvUZXOQujD4m3cB45DyOzzMHcnEEnz6pG6xtbO6 Jb+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:references :in-reply-to:subject:cc:to:from; bh=KGybVctXo+fXnhWEK6uZ+VyX/4dPyZx6J9l5QtRZLRA=; b=vEVE86eLG1Ixk8u5jS85pNLMHwp8UEXtAaLeHVq6SMRB/GABIwHLtxf3MPbFXmPmB/ zMyu2A/glVtzTYdct+eSspkrvKMZH15oU07XTGVpkDExvCo4y9NcL+R7YV1oiP+gUHFP p5RcZGkzVoOiiEnC7w5b8Wo+xuWQ+Q4v/TfoDjG4xHchCH/9Fd9pP5F5JtOj91JfEbC5 mbfhWQX8H9wGbWBp5INJbnXrX5R4kOAt0Y7SbX/5BdGOne/Jp/qbthMfbIQnRT5juH13 y/1dIl2cA0hEWvLEx4nnAmgfpuH7eXvtCHXDLNPSz2YWW8j9zcDVHDlo4x1lwK8onoUf dN4A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n85si3735105oig.191.2020.01.09.08.48.17; Thu, 09 Jan 2020 08:48:30 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730678AbgAIOGN (ORCPT + 99 others); Thu, 9 Jan 2020 09:06:13 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:54422 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728280AbgAIOGM (ORCPT ); Thu, 9 Jan 2020 09:06:12 -0500 Received: from [5.158.153.52] (helo=nanos.tec.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1ipYRV-0003WO-4H; Thu, 09 Jan 2020 15:05:45 +0100 Received: by nanos.tec.linutronix.de (Postfix, from userid 1000) id A3E5F1060CF; Thu, 9 Jan 2020 15:05:44 +0100 (CET) From: Thomas Gleixner To: Christophe Leroy Cc: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , vincenzo.frascino@arm.com, luto@kernel.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [RFC PATCH] powerpc/32: Switch VDSO to C implementation. In-Reply-To: <207cef10-3da8-6a52-139c-0620b21b64af@c-s.fr> References: <8ce3582f7f7da9ff0286ced857e5aa2e5ae6746e.1571662378.git.christophe.leroy@c-s.fr> <95bd2367-8edc-29db-faa3-7729661e05f2@c-s.fr> <439bce37-9c2c-2afe-9c9e-2f500472f9f8@c-s.fr> <207cef10-3da8-6a52-139c-0620b21b64af@c-s.fr> Date: Thu, 09 Jan 2020 15:05:44 +0100 Message-ID: <87d0bslo7b.fsf@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Christophe! Christophe Leroy writes: > In do_hres(), I see: > > cycles = __arch_get_hw_counter(vd->clock_mode); > ns = vdso_ts->nsec; > last = vd->cycle_last; > if (unlikely((s64)cycles < 0)) > return -1; > > __arch_get_hw_counter() returns a u64 values. On the PPC, this is read > from the timebase which is a 64 bits counter. > > Why returning -1 if (s64)cycles < 0 ? Does it means we have to mask out > the most significant bit when reading the HW counter ? Only if you expect the HW counter to reach a value which has bit 63 set. That'd require: uptime counter frequency ~292 years 1GHz ~ 58 years 5GHz assumed that the HW counter starts at 0 when the box is powered on. The reason why this is implemented in this way is that __arch_get_hw_counter() needs a way to express that the clocksource of the moment is not suitable for VDSO so that the syscall fallback gets invoked. Sure we could have used a pointer for the value and a return value indicating the validity, but given the required uptime the resulting code overhead seemed to be not worth it. At least not for me as I'm not planning to be around 58 years from now :) Thanks, tglx