Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp2458492ybl; Thu, 9 Jan 2020 13:08:54 -0800 (PST) X-Google-Smtp-Source: APXvYqxENVHoXZ0dvg2rHJIuHHd/efM1pcUViroP963/BLt0TjOGAJss/j52qWJ9hShuUgtmXNIp X-Received: by 2002:a05:6808:143:: with SMTP id h3mr4945648oie.61.1578604134563; Thu, 09 Jan 2020 13:08:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1578604134; cv=none; d=google.com; s=arc-20160816; b=S0Z2sCEZxB5/BwEnZQzXoJHlqBcdi+XJ0gtcQcXP1dGZeMjAAl55vxsH8EqiO5fJ6h U62XypcaGrtXybGc4jiFRqf8ASR7t85nAU/pstzftNddO2VOdfQ7EPxY2JdPVhMAccnW pJAD+RxklEnJKz5lTgCd50kCMr+U+gOdNBkajQBkQlomd9FKWRsNeQmpQph7u8r/Msb/ NZ7o1iRArAkDGxjdqdU3toWDo9HaLQ3zp3UgfGZ1qKGB0eUPBAkzZFANr1ftFPIQKpKq JRj2USoUM88MHhNfWcWId/4kiHS3/PonVQ8QSnc4yoPTn/q/6Q2/cSYOTDoi4lsP5iNf Lr4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :organization:references:in-reply-to:message-id:subject:cc:to:from :date; bh=lyV5ZBU9oT74I3C6Dj0Yl8voLeFlkBE40haAQFjClfc=; b=T5TDnH2mXKNqd341ZVe3BrjN4LsSDnClNlaGJWscSNkodX1or/SFY9A1ny9XY3BhUk OCyKTECxPk0TpFp02fe66lqQX8+C53PrUN8DP7EnSth6a7BxLmOv/IF14wAIf4TF1SMw WFwuw1lVCp+RNn5CQ0T3TBc7+RPOK+V1NGme2DPv2SLTMLaTEu34OoBOIKLFRSC+CyHH pc7BniVlqqTbWeBzIBi4G7JbikB2ut10QCjtistQXTXTpW7oS6rM2gcb8oW/SN5NB4kV s4buioGDLbT+TU/R3U5aDHHAJNCUMi+sGHecp8+hPOI62t5cAK6IHaiMEyBdx7BcghCL askw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v1si5176403otf.161.2020.01.09.13.08.42; Thu, 09 Jan 2020 13:08:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732641AbgAIPs0 convert rfc822-to-8bit (ORCPT + 99 others); Thu, 9 Jan 2020 10:48:26 -0500 Received: from relay6-d.mail.gandi.net ([217.70.183.198]:55875 "EHLO relay6-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727701AbgAIPs0 (ORCPT ); Thu, 9 Jan 2020 10:48:26 -0500 X-Originating-IP: 91.224.148.103 Received: from xps13 (unknown [91.224.148.103]) (Authenticated sender: miquel.raynal@bootlin.com) by relay6-d.mail.gandi.net (Postfix) with ESMTPSA id E2B82C0013; Thu, 9 Jan 2020 15:48:22 +0000 (UTC) Date: Thu, 9 Jan 2020 16:48:21 +0100 From: Miquel Raynal To: shiva.linuxworks@gmail.com Cc: richard@nod.at, frieder.schrempf@kontron.de, bbrezillon@kernel.org, linux-mtd@lists.infradead.org, dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, vigneshr@ti.com, linux-kernel@vger.kernel.org, Shivamurthy Shastri Subject: Re: [PATCH 1/1] mtd: spinand: Add support for new Micron SPI NAND devices Message-ID: <20200109164821.0e5f0796@xps13> In-Reply-To: <20191209064223.10003-2-sshivamurthy@micron.com> References: <20191209064223.10003-1-sshivamurthy@micron.com> <20191209064223.10003-2-sshivamurthy@micron.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Shiva, shiva.linuxworks@gmail.com wrote on Mon, 9 Dec 2019 07:42:23 +0100: > From: Shivamurthy Shastri > > Add device table for new Micron SPI NAND devices. While at it, add > support to the multi-die selection. Also, generalize the OOB layout > structure and function names. Sorry for the delay. I am fine with this patch mostly, but could we split it please? O/ Disable continuous read feature (one typo, see below). I think this might be considered as a fix. 1/ Generalize the OOB layout structure and function names. 2/ Add support for all the parts. 3/ Add multi-die support (one comment below about that). As a general rule of thumb, small patches, doing one logic change are much easier and quick to review and accept. > +static int micron_select_target(struct spinand_device *spinand, > + unsigned int target) > +{ > + struct spi_mem_op op = SPINAND_SET_FEATURE_OP(0xd0, > + spinand->scratchbuf); > + > + if (target == 1) > + *spinand->scratchbuf = 0x40; Please define 0x40 and explain clearly with a comment that this is multi-die selection. > + > + return spi_mem_exec_op(spinand->spimem, &op); > +} > + [...] > +static int micron_spinand_init(struct spinand_device *spinand) > +{ > + /* > + * M70A series device enables Continuos Read feature on Power-up, > + * which is not supported here. Making this BIT disable will avoid > + * any possible failure. What about: M70A device series enable Continuous Read feature at power-up, which is not supported. Disable this bit to avoid any possible failure. > + */ > + return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, 0); > +} > + > static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = { > .detect = micron_spinand_detect, > + .init = micron_spinand_init, > }; > > const struct spinand_manufacturer micron_spinand_manufacturer = { Thanks, Miquèl