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Fri, 10 Jan 2020 07:17:56 +0000 From: Peng Fan To: "sboyd@kernel.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "festevam@gmail.com" , Abel Vesa , Leonard Crestez CC: "kernel@pengutronix.de" , dl-linux-imx , Aisheng Dong , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Anson Huang , Jacky Bai , Peng Fan Subject: [PATCH V2 3/4] clk: imx: imx8mm: use imx8m_clk_hw_composite_core Thread-Topic: [PATCH V2 3/4] clk: imx: imx8mm: use imx8m_clk_hw_composite_core Thread-Index: AQHVx4YXMxTL9tvflUGSFPY8FST0Gg== Date: Fri, 10 Jan 2020 07:18:01 +0000 Message-ID: <1578640411-16991-4-git-send-email-peng.fan@nxp.com> References: <1578640411-16991-1-git-send-email-peng.fan@nxp.com> In-Reply-To: <1578640411-16991-1-git-send-email-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR06CA0006.apcprd06.prod.outlook.com (2603:1096:202:2e::18) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; 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x-microsoft-antispam-message-info: ilf3yK6WbfyaotCONMB5cXQ3pHNxKQVAiSkcbljKjmWB8m9jvJEAMATUi6+fdjL6Xs+nCMsKYL6FDlekrXuWfTt+3WOq1/5F9lCXj2Avc/KPK33TMUEvTmmozZ79mBFzirRDQ+2X6WGdj0rHYHCP1Wj6B/c4nyH6RKhFyjetQqwWGyHerhqDeV/RUWPKYSkI5blfTpKcJl1+7UfhJEzoY9t/fW85Xq/PU41MGzyjQnurZMVnvxB/Op+fdsJrcj24Q8mMbkqVB2kUeGJftlRXwNxjUTVMQcNlwXsYBwb/VUytGiwyy7J2inC+xHhrFK7eM2+Ie18EJrPNCNwEBJ5dmdxweRKa8xogmRBYTgssxX0L1X3A5qwgZbDqpV5GZu+u17xm3yguHusS4qXvAlcxWmiDviFDOz48AviOujyhaDlMU1QAbZeJmpm/Js3sRH723ldpjEOI0N8vzQuYnvd+pwy/vkuXOPTqbW/EvwWOZIplNma1Um8po6gX/WdF3Ur++szE3mOj3t1v8ud8Qlzi2w== Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d95df21f-3d07-40bb-1737-08d7959d39d5 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jan 2020 07:18:01.1533 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pGRPau8gKp6atl+PtkwXsQbFSBjVrkdyFHA644za3kyMwUrX4eqJ++lGl8iSOOd22Nykn+Dx7mzndnDMxGymvQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB7172 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Peng Fan Use imx8m_clk_hw_composite_core to simplify code. Reviewed-by: Abel Vesa Signed-off-by: Peng Fan --- drivers/clk/imx/clk-imx8mm.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 2ed93fc25087..197ba2cdab7d 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -414,20 +414,13 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) =20 /* Core Slice */ hws[IMX8MM_CLK_A53_SRC] =3D imx_clk_hw_mux2("arm_a53_src", base + 0x8000,= 24, 3, imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)); - hws[IMX8MM_CLK_M4_SRC] =3D imx_clk_hw_mux2("arm_m4_src", base + 0x8080, 2= 4, 3, imx8mm_m4_sels, ARRAY_SIZE(imx8mm_m4_sels)); - hws[IMX8MM_CLK_VPU_SRC] =3D imx_clk_hw_mux2("vpu_src", base + 0x8100, 24,= 3, imx8mm_vpu_sels, ARRAY_SIZE(imx8mm_vpu_sels)); - hws[IMX8MM_CLK_GPU3D_SRC] =3D imx_clk_hw_mux2("gpu3d_src", base + 0x8180,= 24, 3, imx8mm_gpu3d_sels, ARRAY_SIZE(imx8mm_gpu3d_sels)); - hws[IMX8MM_CLK_GPU2D_SRC] =3D imx_clk_hw_mux2("gpu2d_src", base + 0x8200,= 24, 3, imx8mm_gpu2d_sels, ARRAY_SIZE(imx8mm_gpu2d_sels)); hws[IMX8MM_CLK_A53_CG] =3D imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", = base + 0x8000, 28); - hws[IMX8MM_CLK_M4_CG] =3D imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src", bas= e + 0x8080, 28); - hws[IMX8MM_CLK_VPU_CG] =3D imx_clk_hw_gate3("vpu_cg", "vpu_src", base + 0= x8100, 28); - hws[IMX8MM_CLK_GPU3D_CG] =3D imx_clk_hw_gate3("gpu3d_cg", "gpu3d_src", ba= se + 0x8180, 28); - hws[IMX8MM_CLK_GPU2D_CG] =3D imx_clk_hw_gate3("gpu2d_cg", "gpu2d_src", ba= se + 0x8200, 28); hws[IMX8MM_CLK_A53_DIV] =3D imx_clk_hw_divider2("arm_a53_div", "arm_a53_c= g", base + 0x8000, 0, 3); - hws[IMX8MM_CLK_M4_DIV] =3D imx_clk_hw_divider2("arm_m4_div", "arm_m4_cg",= base + 0x8080, 0, 3); - hws[IMX8MM_CLK_VPU_DIV] =3D imx_clk_hw_divider2("vpu_div", "vpu_cg", base= + 0x8100, 0, 3); - hws[IMX8MM_CLK_GPU3D_DIV] =3D imx_clk_hw_divider2("gpu3d_div", "gpu3d_cg"= , base + 0x8180, 0, 3); - hws[IMX8MM_CLK_GPU2D_DIV] =3D imx_clk_hw_divider2("gpu2d_div", "gpu2d_cg"= , base + 0x8200, 0, 3); + + hws[IMX8MM_CLK_M4_DIV] =3D imx8m_clk_hw_composite_core("arm_m4_div", imx8= mm_m4_sels, base + 0x8080); + hws[IMX8MM_CLK_VPU_DIV] =3D imx8m_clk_hw_composite_core("vpu_div", imx8mm= _vpu_sels, base + 0x8100); + hws[IMX8MM_CLK_GPU3D_DIV] =3D imx8m_clk_hw_composite_core("gpu3d_div", im= x8mm_gpu3d_sels, base + 0x8180); + hws[IMX8MM_CLK_GPU2D_DIV] =3D imx8m_clk_hw_composite_core("gpu2d_div", im= x8mm_gpu2d_sels, base + 0x8200); =20 /* BUS */ hws[IMX8MM_CLK_MAIN_AXI] =3D imx8m_clk_hw_composite_critical("main_axi", = imx8mm_main_axi_sels, base + 0x8800); --=20 2.16.4