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From:   Peng Fan <peng.fan@nxp.com>
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Subject: [PATCH] arm64: dts: imx8mn: Init rates and parents configs for clocks
Thread-Topic: [PATCH] arm64: dts: imx8mn: Init rates and parents configs for
 clocks
Thread-Index: AQHVx4ZxYo+CJ71kh0mLSYhdPwN+wA==
Date:   Fri, 10 Jan 2020 07:20:31 +0000
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From: Peng Fan <peng.fan@nxp.com>

Add the initial configuration for clocks that need default parent and rate
setting.

NoC sources from SYS PLL3, running at 600MHz. Audio AHB/IPG clks needs
to run at 400MHz for better performance.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt=
s/freescale/imx8mn.dtsi
index a44b5438e842..0a62a478a930 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -379,6 +379,16 @@
 					 <&clk_ext3>, <&clk_ext4>;
 				clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 					      "clk_ext3", "clk_ext4";
+				assigned-clocks =3D <&clk IMX8MN_CLK_NOC>,
+						<&clk IMX8MN_CLK_AUDIO_AHB>,
+						<&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
+						<&clk IMX8MN_SYS_PLL3>;
+				assigned-clock-parents =3D <&clk IMX8MN_SYS_PLL3_OUT>,
+							 <&clk IMX8MN_SYS_PLL1_800M>;
+				assigned-clock-rates =3D <0>,
+							<400000000>,
+							<400000000>,
+							<600000000>;
 			};
=20
 			src: reset-controller@30390000 {
--=20
2.16.4