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Mon, 13 Jan 2020 06:39:09 +0000 From: Yash Shah To: paul.walmsley@sifive.com, palmer@dabbelt.com Cc: aou@eecs.berkeley.edu, allison@lohutok.net, alexios.zavras@intel.com, gregkh@linuxfoundation.org, tglx@linutronix.de, bp@suse.de, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah Subject: [PATCH v3 2/2] riscv: Add support to determine no. of L2 cache way enabled Date: Mon, 13 Jan 2020 12:08:20 +0530 Message-Id: <1578897500-23897-3-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578897500-23897-1-git-send-email-yash.shah@sifive.com> References: <1578897500-23897-1-git-send-email-yash.shah@sifive.com> Content-Type: text/plain X-ClientProxiedBy: PN1PR01CA0081.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::21) To CH2PR13MB3368.namprd13.prod.outlook.com (2603:10b6:610:2c::26) MIME-Version: 1.0 Received: from dhananjayk-PowerEdge-R620.open-silicon.com (114.143.65.226) by PN1PR01CA0081.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2623.11 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: 2U6fIBz93qIdgznRq6c73N8PQPnEeRH5nsz/7JYTEd4unp2+MhJo3Osss8rJdBHdTXJlksfY7XXzB8M0IuhYcs+W3aA2U+VqpL1EWDHWq0ak9IXFWAdpUpbTP0Vsmx7lG0rJUoGHOwcery7A0x+289Div8TzO58kvFUME4OsHfjVDKz6+4Y1BVm0D20EnHXf7O8WYxhs4QAzAMXvF8UEh5/i8EB9HNHWkrMGzDgBlxI6m7egI+Fd3T7EtuLafKdRj/H4i9fTzwmEcO5z1drqkTBL4ZMbt/TBA6Flf5mL882Y+EK0j1CDJ1h+ZwAGr2nYKzBijcSrbZZBDJLZjJeEIIn+F+ANjOGORt25axTib+M7nafXDgu+qY/6QMLNHC3HqWdV50fXM02ib+De8LcbC5WYLo3qMoS9NzkKB8hBk6rt5FvcpjbuStFhydPLzBIO X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: 40a152fb-4669-4d52-bb4a-08d797f34b0f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2020 06:39:09.0842 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2onyMJ6jSSEqFEILKpw6z81Pu9yCtvnQT0dnK1fprTk0YoqIvdjKEVQ8Zy8ap5VaYbOd4sf+MHZGgs5/8I1j6w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR13MB3317 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah --- drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ include/soc/sifive/sifive_l2_cache.h | 2 ++ 2 files changed, 40 insertions(+) diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index a506939..8741885 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #define SIFIVE_L2_DIRECCFIX_LOW 0x100 @@ -31,6 +33,7 @@ static void __iomem *l2_base; static int g_irq[SIFIVE_L2_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops l2_cache_ops; enum { DIR_CORR = 0, @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb) } EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); +int sifive_l2_largest_wayenabled(void) +{ + return readl(l2_base + SIFIVE_L2_WAYENABLE); +} + +static ssize_t number_of_ways_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", sifive_l2_largest_wayenabled()); +} + +static DEVICE_ATTR_RO(number_of_ways_enabled); + +static struct attribute *priv_attrs[] = { + &dev_attr_number_of_ways_enabled.attr, + NULL, +}; + +static const struct attribute_group priv_attr_group = { + .attrs = priv_attrs, +}; + +const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) +{ + /* We want to use private group for L2 cache only */ + if (this_leaf->level == 2) + return &priv_attr_group; + else + return NULL; +} + static irqreturn_t l2_int_handler(int irq, void *device) { unsigned int add_h, add_l; @@ -170,6 +205,9 @@ static int __init sifive_l2_init(void) l2_config_read(); + l2_cache_ops.get_priv_group = l2_get_priv_group; + riscv_set_cacheinfo_ops(&l2_cache_ops); + #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_l2_cache.h index 92ade10..55feff5 100644 --- a/include/soc/sifive/sifive_l2_cache.h +++ b/include/soc/sifive/sifive_l2_cache.h @@ -10,6 +10,8 @@ extern int register_sifive_l2_error_notifier(struct notifier_block *nb); extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb); +int sifive_l2_largest_wayenabled(void); + #define SIFIVE_L2_ERR_TYPE_CE 0 #define SIFIVE_L2_ERR_TYPE_UE 1 -- 2.7.4