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[209.132.180.67]) by mx.google.com with ESMTP id b4si6263408oib.70.2020.01.13.10.25.06; Mon, 13 Jan 2020 10:25:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=F3cpbs7o; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728841AbgAMSXx (ORCPT + 99 others); Mon, 13 Jan 2020 13:23:53 -0500 Received: from mail-il1-f193.google.com ([209.85.166.193]:44127 "EHLO mail-il1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728633AbgAMSXx (ORCPT ); Mon, 13 Jan 2020 13:23:53 -0500 Received: by mail-il1-f193.google.com with SMTP id z12so8968388iln.11 for ; Mon, 13 Jan 2020 10:23:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=GdPsIU0hG7suGBkyMM6A9F/OIU18NvlvaZKX62ICZx8=; b=F3cpbs7os6RE8zrBTuxlPO7wpMoMKwrvMNGtUUy7U6PmvdA/3IuWrXhdlDTRvA2nfq VkWS495dAWj/I8us3RuMz8J3YM4xEJXTLHgxpKlzGdWjYTafRlf1MJrve5FE6GLKsYEd 2w83Ziko98Ggm9AWNE5NwXzIynltxqB5/FBPA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=GdPsIU0hG7suGBkyMM6A9F/OIU18NvlvaZKX62ICZx8=; b=ZtPwDaburFq8p3QhsC0AzZzE1ltPtvUWWkjiCgJ+vQSyMcImXmH4snHqZmeSFfPFA9 khrzu+euqhZpB51qdDzc7fYgIHZEnXHmpL0kUI5D/q/hmke3iZ/a9oIPdNx0KZ0N/4R+ p/18hyVCjfKN9EYdxoeWBu2yQinlQxaFzPAceykrXmA2NZrqR9qqpa4kJjSOT7ZN5gNq BYJAsTGeesq5TwZ9R6Wy+7jfsBZvB6ORSmlUljjdQDwtOVglmvBZA31ubrbJ4Ep1nS1H sM5dhzyQEHKMCOSYo7sOsxPpofkmrqDRZTnaMiDTjK6viv2OrIyO4V7iVRn9S7yQ98N+ jaJw== X-Gm-Message-State: APjAAAXPm0/APEveWwAKN1rJatLdhXib7LLFxrLXpBvmAkovyl/7J6fb G/rjB6sDPK1FHAkygwYhGt11BoovuHUo0EGMxdwUlA== X-Received: by 2002:a92:d708:: with SMTP id m8mr15406018iln.244.1578939832899; Mon, 13 Jan 2020 10:23:52 -0800 (PST) MIME-Version: 1.0 References: <20200113153605.52350-1-brian@brkho.com> <20200113153605.52350-2-brian@brkho.com> <20200113175522.GD26711@jcrouse1-lnx.qualcomm.com> In-Reply-To: <20200113175522.GD26711@jcrouse1-lnx.qualcomm.com> From: Rob Clark Date: Mon, 13 Jan 2020 10:23:42 -0800 Message-ID: Subject: Re: [Freedreno] [PATCH 1/2] drm/msm: Add a GPU-wide wait queue To: Brian Ho , freedreno , robdclark@chromium.org, David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Rob Clark , Daniel Vetter , Kristian Kristensen , Sean Paul Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 13, 2020 at 9:55 AM Jordan Crouse wrote: > > On Mon, Jan 13, 2020 at 10:36:04AM -0500, Brian Ho wrote: > > This wait queue is signaled on all IRQs for a given GPU and will be > > used as part of the new MSM_WAIT_IOVA ioctl so userspace can sleep > > until the value at a given iova reaches a certain condition. > > > > Signed-off-by: Brian Ho > > --- > > drivers/gpu/drm/msm/msm_gpu.c | 4 ++++ > > drivers/gpu/drm/msm/msm_gpu.h | 3 +++ > > 2 files changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c > > index a052364a5d74..d7310c1336e5 100644 > > --- a/drivers/gpu/drm/msm/msm_gpu.c > > +++ b/drivers/gpu/drm/msm/msm_gpu.c > > @@ -779,6 +779,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, > > static irqreturn_t irq_handler(int irq, void *data) > > { > > struct msm_gpu *gpu = data; > > + wake_up_all(&gpu->event); > > + > > I suppose it is intentional to have this happen on *all* interrupts because you > might be using the CP interrupts for fun and profit and you don't want to plumb > in callbacks? I suppose it is okay to do this for all interrupts (including > errors) but if we're spending a lot of time here we might want to only trigger > on certain IRQs. Was just talking to Kristian about GPU hangs.. and I suspect we might want the ioctl to return an error if there is a gpu reset (so that userspace can use the robustness uapi to test if the gpu reset was something it cares about, etc) Which is as good as a reason as I can think of the wake_up_all() on all irqs.. BR, -R > > > return gpu->funcs->irq(gpu); > > } > > > > @@ -871,6 +873,8 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, > > > > spin_lock_init(&gpu->perf_lock); > > > > + init_waitqueue_head(&gpu->event); > > + > > > > /* Map registers: */ > > gpu->mmio = msm_ioremap(pdev, config->ioname, name); > > diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h > > index ab8f0f9c9dc8..60562f065dbc 100644 > > --- a/drivers/gpu/drm/msm/msm_gpu.h > > +++ b/drivers/gpu/drm/msm/msm_gpu.h > > @@ -104,6 +104,9 @@ struct msm_gpu { > > > > struct msm_gem_address_space *aspace; > > > > + /* GPU-wide wait queue that is signaled on all IRQs */ > > + wait_queue_head_t event; > > + > > /* Power Control: */ > > struct regulator *gpu_reg, *gpu_cx; > > struct clk_bulk_data *grp_clks; > > -- > > 2.25.0.rc1.283.g88dfdc4193-goog > > > > _______________________________________________ > > Freedreno mailing list > > Freedreno@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/freedreno > > -- > The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project