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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Shawn Guo <shawnguo@kernel.org>, Peng Fan <peng.fan@nxp.com>
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        Aisheng Dong <aisheng.dong@nxp.com>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Anson Huang <anson.huang@nxp.com>, Jacky Bai <ping.bai@nxp.com>
Subject: Re: [PATCH 1/3] clk: imx: pll14xx: avoid modify dram pll
Thread-Topic: [PATCH 1/3] clk: imx: pll14xx: avoid modify dram pll
Thread-Index: AQHVvvFWN8I9RWVOxUWrR8yNvTfk6g==
Date:   Tue, 14 Jan 2020 00:11:48 +0000
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On 12.01.2020 04:33, Shawn Guo wrote:=0A=
> On Mon, Dec 30, 2019 at 09:13:00AM +0000, Peng Fan wrote:=0A=
>> From: Peng Fan <peng.fan@nxp.com>=0A=
>>=0A=
>> The dram pll is only expected to be modified in firmware,=0A=
>> so we should only support read clk frequency in Linux Kernel.=0A=
>>=0A=
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>=0A=
> =0A=
> @Leonard, do you agree?=0A=
=0A=
I'm not sure this improves anything.=0A=
=0A=
As far as I understand the only way this could be a problem is if a =0A=
driver deliberately does clk_set_rate on the dram pll and this shouldn't =
=0A=
happen.=0A=
=0A=
There is an infinite number of ways for clock consumers to break the =0A=
system by manipulating clocks and providers don't need to guard against =0A=
every scenario.=0A=
=0A=
>> ---=0A=
>>   drivers/clk/imx/clk-pll14xx.c | 11 ++++++++---=0A=
>>   1 file changed, 8 insertions(+), 3 deletions(-)=0A=
>>=0A=
>> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx=
.c=0A=
>> index 5b0519a81a7a..9288b21d4d59 100644=0A=
>> --- a/drivers/clk/imx/clk-pll14xx.c=0A=
>> +++ b/drivers/clk/imx/clk-pll14xx.c=0A=
>> @@ -69,8 +69,6 @@ struct imx_pll14xx_clk imx_1443x_pll =3D {=0A=
>>   =0A=
>>   struct imx_pll14xx_clk imx_1443x_dram_pll =3D {=0A=
>>   	.type =3D PLL_1443X,=0A=
>> -	.rate_table =3D imx_pll1443x_tbl,=0A=
>> -	.rate_count =3D ARRAY_SIZE(imx_pll1443x_tbl),=0A=
>>   	.flags =3D CLK_GET_RATE_NOCACHE,=0A=
>>   };=0A=
>>   =0A=
>> @@ -376,6 +374,10 @@ static const struct clk_ops clk_pll1443x_ops =3D {=
=0A=
>>   	.set_rate	=3D clk_pll1443x_set_rate,=0A=
>>   };=0A=
>>   =0A=
>> +static const struct clk_ops clk_pll1443x_min_ops =3D {=0A=
>> +	.recalc_rate	=3D clk_pll1443x_recalc_rate,=0A=
>> +};=0A=
>> +=0A=
>>   struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent=
_name,=0A=
>>   				  void __iomem *base,=0A=
>>   				  const struct imx_pll14xx_clk *pll_clk)=0A=
>> @@ -403,7 +405,10 @@ struct clk_hw *imx_clk_hw_pll14xx(const char *name,=
 const char *parent_name,=0A=
>>   			init.ops =3D &clk_pll1416x_ops;=0A=
>>   		break;=0A=
>>   	case PLL_1443X:=0A=
>> -		init.ops =3D &clk_pll1443x_ops;=0A=
>> +		if (!pll_clk->rate_table)=0A=
>> +			init.ops =3D &clk_pll1443x_min_ops;=0A=
>> +		else=0A=
>> +			init.ops =3D &clk_pll1443x_ops;=0A=
>>   		break;=0A=
>>   	default:=0A=
>>   		pr_err("%s: Unknown pll type for pll clk %s\n",=0A=