Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp4896945ybl;
        Mon, 13 Jan 2020 23:28:25 -0800 (PST)
X-Google-Smtp-Source: APXvYqyEYVBE5FB1btTr4jw8LWCLbUI++O9q88eB3EB8rgjsdZiTQxbEo3NqeRG1sLTrJGpuhy5+
X-Received: by 2002:aca:3141:: with SMTP id x62mr15041590oix.108.1578986905659;
        Mon, 13 Jan 2020 23:28:25 -0800 (PST)
ARC-Seal: i=1; a=rsa-sha256; t=1578986905; cv=none;
        d=google.com; s=arc-20160816;
        b=OyYniNpqkT5h3tOPe8FT0t3uNWr1/P/GLN3QXPQr2B8DqDGxVlEGFkQGHOSeeRivxP
         tug3nUqqecsSm+m+oHZZGFUWR/yQFS90+HBZe6W3no6FXIzPbZxKFeePOdsqVciI0jQ8
         uQ3t++cjJC6sh8z2EQSN49DPaWCCvaV09oP0dEhJUdKglQSSngoqoJb8GCEvmYX2cXB5
         zA7iobLK5vzrEo976HXAOjDrOOBOeNNo5gloKp8KfzdY/pJx3lBl8OJEOCR3d3zPG/Kh
         +dDTz6GiOmUWG/siKaA1LAyC7bnXjUlnJrKJuQQK9JOI2MUAux2MToLzjPwIlbEVlU/P
         c9+w==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:dkim-signature:mime-version:references
         :in-reply-to:message-id:date:subject:cc:to:from;
        bh=Z3ACX3vP5nNFEx8B7eX+Er9D7XJtGr/zcelaygn+3Bo=;
        b=u+//MDlFgf2jndeVxPRs8GcadJYdLN8A8h+XkPnoovYPGEVg25AOEqom2CqnwRJe68
         HDUZgJmMjlCL8weX5vJGPQt6qfago3RMkxH8NWPt/5LwpUfgVmNQU8WVFiDYImtCTuq3
         usVBTEilne5hd0gqaf3Pb0PS6APBXPqH4F15BG0gW265gsCemtuxhHhvNWOk5J62/ZMa
         MBaxJK8ys0CAgkxy3fF9T8tgwRFxPGJh3KMvQFV5zt8B0eJUwZkNDtGTh5hdI5ZNxLXP
         yWeTquUA4HKOa3dmaNJp9i145FQB1wlShqmnLrsMoVIITnS4+5ixczQ+igAXDR59kZt8
         tZLQ==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b="UH3Zr/La";
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id u84si7386956oib.34.2020.01.13.23.28.14;
        Mon, 13 Jan 2020 23:28:25 -0800 (PST)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b="UH3Zr/La";
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1729420AbgANH0D (ORCPT <rfc822;gklkml16@gmail.com> + 99 others);
        Tue, 14 Jan 2020 02:26:03 -0500
Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:13865 "EHLO
        hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1729039AbgANHYf (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Tue, 14 Jan 2020 02:24:35 -0500
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5e1d6c9e0000>; Mon, 13 Jan 2020 23:24:14 -0800
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Mon, 13 Jan 2020 23:24:34 -0800
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Mon, 13 Jan 2020 23:24:34 -0800
Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com
 (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 14 Jan
 2020 07:24:33 +0000
Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com
 (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend
 Transport; Tue, 14 Jan 2020 07:24:34 +0000
Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.169.242]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5e1d6cb10000>; Mon, 13 Jan 2020 23:24:33 -0800
From:   Sowjanya Komatineni <skomatineni@nvidia.com>
To:     <skomatineni@nvidia.com>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>, <broonie@kernel.org>,
        <lgirdwood@gmail.com>, <perex@perex.cz>, <tiwai@suse.com>,
        <digetx@gmail.com>, <mperttunen@nvidia.com>,
        <gregkh@linuxfoundation.org>, <sboyd@kernel.org>,
        <robh+dt@kernel.org>, <mark.rutland@arm.com>
CC:     <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,
        <spujar@nvidia.com>, <josephl@nvidia.com>,
        <daniel.lezcano@linaro.org>, <mmaddireddy@nvidia.com>,
        <markz@nvidia.com>, <devicetree@vger.kernel.org>,
        <linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
Subject: [PATCH v8 07/22] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
Date:   Mon, 13 Jan 2020 23:24:12 -0800
Message-ID: <1578986667-16041-8-git-send-email-skomatineni@nvidia.com>
X-Mailer: git-send-email 2.7.4
In-Reply-To: <1578986667-16041-1-git-send-email-skomatineni@nvidia.com>
References: <1578986667-16041-1-git-send-email-skomatineni@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1578986654; bh=Z3ACX3vP5nNFEx8B7eX+Er9D7XJtGr/zcelaygn+3Bo=;
        h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
         In-Reply-To:References:X-NVConfidentiality:MIME-Version:
         Content-Type;
        b=UH3Zr/LaYVVJA+tp7yRj23j7K48qT5ggBbtUxqW+AABmrbs8ZASLgIeA26MJKK6q+
         F7PrBKATCu0DQ/FS5QW2RSAQFdKL/IuvURWBHq7wVnmaxVELNao1nzEYJWIf9nNCWW
         eXNo4zyScE/9poyCcO+c3/sf+pZhqDxECrisx6kEPzxI+bloTWj5wel5YNa6MyU+mW
         8I/n4uI2jmAmIGrlzKssbou5eSJTWVhFC2c5kBWk4oFf2gJIq3Cp0/Du+Io1Qg4UQW
         VhU83QrfZ9C/B6fpvMuGLwYtV4i6ExZCzd1CZiwhhIUFRfr8nzHG/60JnYUgNEtdB6
         5qAF/sDvk0JNg==
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Tegra PMC has 3 clocks clk_out_1, clk_out_2, and clk_out_3.

This patch documents PMC clock bindings and adds a header defining
Tegra PMC clock ids.

Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 12 ++++++++++++
 include/dt-bindings/soc/tegra-pmc.h                       | 15 +++++++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 include/dt-bindings/soc/tegra-pmc.h

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 3ff34b348141..5b5c42a00264 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -40,6 +40,15 @@ properties:
       Must contain an entry for each entry in clock-names.
       See ../clocks/clocks-bindings.txt for details.
 
+  '#clock-cells':
+    const: 1
+    description:
+      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
+      Consumer of PMC clock should specify the desired clock by having
+      the clock ID in its "clocks" phandle cell with pmc clock provider.
+      See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
+      clock IDs.
+
   '#interrupt-cells':
     const: 2
     description:
@@ -296,6 +305,7 @@ required:
   - reg
   - clock-names
   - clocks
+  - '#clock-cells'
 
 dependencies:
   "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
@@ -307,12 +317,14 @@ examples:
 
     #include <dt-bindings/clock/tegra210-car.h>
     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
+    #include <dt-bindings/soc/tegra-pmc.h>
 
     tegra_pmc: pmc@7000e400 {
               compatible = "nvidia,tegra210-pmc";
               reg = <0x0 0x7000e400 0x0 0x400>;
               clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
               clock-names = "pclk", "clk32k_in";
+              #clock-cells = <1>;
 
               nvidia,invert-interrupt;
               nvidia,suspend-mode = <0>;
diff --git a/include/dt-bindings/soc/tegra-pmc.h b/include/dt-bindings/soc/tegra-pmc.h
new file mode 100644
index 000000000000..f7c866404456
--- /dev/null
+++ b/include/dt-bindings/soc/tegra-pmc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_SOC_TEGRA_PMC_H
+#define _DT_BINDINGS_SOC_TEGRA_PMC_H
+
+#define TEGRA_PMC_CLK_OUT_1		0
+#define TEGRA_PMC_CLK_OUT_2		1
+#define TEGRA_PMC_CLK_OUT_3		2
+
+#define TEGRA_PMC_CLK_MAX		3
+
+#endif	/* _DT_BINDINGS_SOC_TEGRA_PMC_H */
-- 
2.7.4