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Date:   Tue, 14 Jan 2020 14:23:55 +0000
To:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
From:   Krzysztof Piecuch <piecuch@protonmail.com>
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Reply-To: Krzysztof Piecuch <piecuch@protonmail.com>
Subject: [PATCH] x86/tsc: Add tsc_guess flag disabling CPUID.16h use for tsc calibration
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Changing base clock frequency directly impacts tsc hz but not CPUID.16h
values. An overclocked CPU supporting CPUID.16h and partial CPUID.15h
support will set tsc hz according to "best guess" given by CPUID.16h
relying on tsc_refine_calibration_work to give better numbers later.
tsc_refine_calibration_work will refuse to do its work when the outcome is
off the early tsc hz value by more than 1% which is certain to happen on an
overclocked system.

Signed-off-by: Krzysztof Piecuch <piecuch@protonmail.com>
---
 Documentation/admin-guide/kernel-parameters.txt |  6 ++++++
 arch/x86/kernel/tsc.c                           | 12 ++++++++++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio=
n/admin-guide/kernel-parameters.txt
index ade4e6ec23e0..54ae9e153a19 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -4905,6 +4905,12 @@
 =09=09=09interruptions from clocksource watchdog are not
 =09=09=09acceptable).

+=09tsc_guess=3D=09[X86,INTEL] Don't use data provided by CPUID.16h during
+=09=09=09early tsc calibration. Disabling this may be useful for
+=09=09=09CPUs with altered base clocks.
+=09=09=09Format: <bool> (1/Y/y=3Denable, 0/N/n=3Ddisable)
+=09=09=09default: enabled
+
 =09tsx=3D=09=09[X86] Control Transactional Synchronization
 =09=09=09Extensions (TSX) feature in Intel processors that
 =09=09=09support TSX control.
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 7e322e2daaf5..a807c33a3d41 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -59,6 +59,13 @@ struct cyc2ns {

 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);

+static bool _read_mostly tsc_guess =3D 1;
+static int __init tsc_guess_setup(char *buf)
+{
+=09return strtobool(buf, &tsc_guess);
+}
+early_param("tsc_guess", tsc_guess_setup);
+
 __always_inline void cyc2ns_read_begin(struct cyc2ns_data *data)
 {
 =09int seq, idx;
@@ -654,7 +661,8 @@ unsigned long native_calibrate_tsc(void)
 =09 * clock, but we can easily calculate it to a high degree of accuracy
 =09 * by considering the crystal ratio and the CPU speed.
 =09 */
-=09if (crystal_khz =3D=3D 0 && boot_cpu_data.cpuid_level >=3D 0x16) {
+=09if (crystal_khz =3D=3D 0 && tsc_guess &&
+=09=09boot_cpu_data.cpuid_level >=3D 0x16) {
 =09=09unsigned int eax_base_mhz, ebx, ecx, edx;

 =09=09cpuid(0x16, &eax_base_mhz, &ebx, &ecx, &edx);
@@ -692,7 +700,7 @@ static unsigned long cpu_khz_from_cpuid(void)
 =09if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL)
 =09=09return 0;

-=09if (boot_cpu_data.cpuid_level < 0x16)
+=09if (boot_cpu_data.cpuid_level < 0x16 || !tsc_guess)
 =09=09return 0;

 =09eax_base_mhz =3D ebx_max_mhz =3D ecx_bus_mhz =3D edx =3D 0;
--
2.20.1