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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Shawn Guo <shawnguo@kernel.org>, Peng Fan <peng.fan@nxp.com>
CC:     Lucas Stach <l.stach@pengutronix.de>,
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        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
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        Abel Vesa <abel.vesa@nxp.com>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Anson Huang <anson.huang@nxp.com>, Jacky Bai <ping.bai@nxp.com>
Subject: Re: [PATCH V2 2/4] clk: imx: imx8mq: use imx8m_clk_hw_composite_core
Thread-Topic: [PATCH V2 2/4] clk: imx: imx8mq: use imx8m_clk_hw_composite_core
Thread-Index: AQHVx4YVaHYUgIfOpEylrWn5NhhQ0A==
Date:   Wed, 15 Jan 2020 11:48:11 +0000
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On 2020-01-15 1:12 PM, Shawn Guo wrote:=0A=
> On Tue, Jan 14, 2020 at 04:49:20PM +0000, Leonard Crestez wrote:=0A=
>> On 10.01.2020 09:17, Peng Fan wrote:=0A=
>>> From: Peng Fan <peng.fan@nxp.com>=0A=
>>>=0A=
>>> Use imx8m_clk_hw_composite_core to simplify code.=0A=
>>>=0A=
>>> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>=0A=
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>=0A=
>>> ---=0A=
>>>    drivers/clk/imx/clk-imx8mq.c | 19 +++++--------------=0A=
>>>    1 file changed, 5 insertions(+), 14 deletions(-)=0A=
>>>=0A=
>>> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.=
c=0A=
>>> index 4c0edca1a6d0..b031183ff427 100644=0A=
>>> --- a/drivers/clk/imx/clk-imx8mq.c=0A=
>>> +++ b/drivers/clk/imx/clk-imx8mq.c=0A=
>>> @@ -403,22 +403,13 @@ static int imx8mq_clocks_probe(struct platform_de=
vice *pdev)=0A=
>>>    =0A=
>>>    	/* CORE */=0A=
>>>    	hws[IMX8MQ_CLK_A53_SRC] =3D imx_clk_hw_mux2("arm_a53_src", base + 0=
x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));=0A=
>>> -	hws[IMX8MQ_CLK_M4_SRC] =3D imx_clk_hw_mux2("arm_m4_src", base + 0x808=
0, 24, 3, imx8mq_arm_m4_sels, ARRAY_SIZE(imx8mq_arm_m4_sels));=0A=
>>> -	hws[IMX8MQ_CLK_VPU_SRC] =3D imx_clk_hw_mux2("vpu_src", base + 0x8100,=
 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels));=0A=
>>> -	hws[IMX8MQ_CLK_GPU_CORE_SRC] =3D imx_clk_hw_mux2("gpu_core_src", base=
 + 0x8180, 24, 3,  imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels));=
=0A=
>>> -	hws[IMX8MQ_CLK_GPU_SHADER_SRC] =3D imx_clk_hw_mux2("gpu_shader_src", =
base + 0x8200, 24, 3, imx8mq_gpu_shader_sels,  ARRAY_SIZE(imx8mq_gpu_shader=
_sels));=0A=
>>> -=0A=
>>>    	hws[IMX8MQ_CLK_A53_CG] =3D imx_clk_hw_gate3_flags("arm_a53_cg", "ar=
m_a53_src", base + 0x8000, 28, CLK_IS_CRITICAL);=0A=
>>> -	hws[IMX8MQ_CLK_M4_CG] =3D imx_clk_hw_gate3("arm_m4_cg", "arm_m4_src",=
 base + 0x8080, 28);=0A=
>>> -	hws[IMX8MQ_CLK_VPU_CG] =3D imx_clk_hw_gate3("vpu_cg", "vpu_src", base=
 + 0x8100, 28);=0A=
>>> -	hws[IMX8MQ_CLK_GPU_CORE_CG] =3D imx_clk_hw_gate3("gpu_core_cg", "gpu_=
core_src", base + 0x8180, 28);=0A=
>>> -	hws[IMX8MQ_CLK_GPU_SHADER_CG] =3D imx_clk_hw_gate3("gpu_shader_cg", "=
gpu_shader_src", base + 0x8200, 28);=0A=
>>> -=0A=
>>>    	hws[IMX8MQ_CLK_A53_DIV] =3D imx_clk_hw_divider2("arm_a53_div", "arm=
_a53_cg", base + 0x8000, 0, 3);=0A=
>>> -	hws[IMX8MQ_CLK_M4_DIV] =3D imx_clk_hw_divider2("arm_m4_div", "arm_m4_=
cg", base + 0x8080, 0, 3);=0A=
>>> -	hws[IMX8MQ_CLK_VPU_DIV] =3D imx_clk_hw_divider2("vpu_div", "vpu_cg", =
base + 0x8100, 0, 3);=0A=
>>> -	hws[IMX8MQ_CLK_GPU_CORE_DIV] =3D imx_clk_hw_divider2("gpu_core_div", =
"gpu_core_cg", base + 0x8180, 0, 3);=0A=
>>> -	hws[IMX8MQ_CLK_GPU_SHADER_DIV] =3D imx_clk_hw_divider2("gpu_shader_di=
v", "gpu_shader_cg", base + 0x8200, 0, 3);=0A=
>>> +=0A=
>>> +	hws[IMX8MQ_CLK_M4_DIV] =3D imx8m_clk_hw_composite_core("arm_m4_div", =
imx8mq_arm_m4_sels, base + 0x8080);=0A=
>>> +	hws[IMX8MQ_CLK_VPU_DIV] =3D imx8m_clk_hw_composite_core("vpu_div", im=
x8mq_vpu_sels, base + 0x8100);=0A=
>>> +	hws[IMX8MQ_CLK_GPU_CORE_DIV] =3D imx8m_clk_hw_composite_core("gpu_cor=
e_div", imx8mq_gpu_core_sels, base + 0x8180);=0A=
>>> +	hws[IMX8MQ_CLK_GPU_SHADER_DIV] =3D imx8m_clk_hw_composite("gpu_shader=
_div", imx8mq_gpu_shader_sels, base + 0x8200);=0A=
>>>    =0A=
>>>    	/* BUS */=0A=
>>>    	hws[IMX8MQ_CLK_MAIN_AXI] =3D imx8m_clk_hw_composite_critical("main_=
axi", imx8mq_main_axi_sels, base + 0x8800);=0A=
>>=0A=
>> Collapsing _SRC _CG into _DIV is an useful simplification but it=0A=
>> technically breaks DT compatibility rules.=0A=
>>=0A=
>> Inside imx8mq.dtsi there are clock assignments for=0A=
>> IMX8MQ_CLK_GPU_CORE_SRC and IMX8MQ_CLK_GPU_SHADER_SRC which no longer=0A=
>> exist so those assignments don't take effect.=0A=
> =0A=
> We do not want to break existing DTBs for this case.  Patches dropped.=0A=
=0A=
Sorry. I think DT compatibility could be maintained by adding =0A=
assignments like this:=0A=
=0A=
	hws[IMX8MQ_CLK_GPU_CORE_SRC] =3D hws[IMX8MQ_CLK_GPU_CORE_DIV];=0A=
=0A=
If all the old clocks are aliased to the new composite then all =0A=
currently valid set_rate and set_parent calls would still have the same =0A=
effect.=0A=
=0A=
It would also mean that you can set_rate on the mux and set_parent on =0A=
the div but that should be harmless: an enhancement instead of a =0A=
compat-breaking change.=0A=
=0A=
--=0A=
Regards,=0A=
Leonard=0A=