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Date:   Wed, 15 Jan 2020 13:49:18 -0800
From:   "Luck, Tony" <tony.luck@intel.com>
To:     Josh Poimboeuf <jpoimboe@redhat.com>
Cc:     Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
        "H. Peter Anvin" <hpa@zytor.com>, x86@kernel.org,
        Michal Hocko <mhocko@suse.com>, linux-kernel@vger.kernel.org,
        Neelima Krishnan <neelima.krishnan@intel.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH] x86/cpu: Update cached HLE state on write to
 TSX_CTRL_CPUID_CLEAR
Message-ID: <20200115214918.GA13375@agluck-desk2.amr.corp.intel.com>
References: <2529b99546294c893dfa1c89e2b3e46da3369a59.1578685425.git.pawan.kumar.gupta@linux.intel.com>
 <20200115211513.mxzembrm4hf44d6j@treble>
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On Wed, Jan 15, 2020 at 03:15:13PM -0600, Josh Poimboeuf wrote:
> From the Intel TAA deep dive page [1], it says:
> 
>   "On processors that enumerate IA32_ARCH_CAPABILITIES[TSX_CTRL] (bit
>    7)=1, HLE prefix hints are always ignored."
> 
> So if the CPU has IA32_TSX_CTRL, HLE is implicitly disabled, so why
> would the HLE bit have been set in CPUID in the first place?
> 
> [1] https://software.intel.com/security-software-guidance/insights/deep-dive-intel-transactional-synchronization-extensions-intel-tsx-asynchronous-abort

IIRC some VMM folks asked to not make gratuitous to CPUID feature
enumeration because it complicates setting up pools of systems.

-Tony