Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp8395630ybl; Thu, 16 Jan 2020 16:02:22 -0800 (PST) X-Google-Smtp-Source: APXvYqwg4ObnE3sb9hJRgvrWvF1a1nZ1FzwfTAAtQBjDFMbCRkz8/MEgwtkcUbUloUSbjCM0wPQd X-Received: by 2002:aca:33d5:: with SMTP id z204mr1385202oiz.120.1579219342477; Thu, 16 Jan 2020 16:02:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1579219342; cv=none; d=google.com; s=arc-20160816; b=tCWYkvm6vC6cRXp4rAdd79TJD8IJ34cRWNFt9ZWQwx6Zo89VvM8JCmyPRlSgFROFdc JYv1ZYxgDIcoeJ371UCMipMqAiEGd8Oqey4SDp87/y/0pOvrinrjgy5L8wwfvOXa06xg qP0ei8AMwTYzMnoUYQQk42yF1+8S491+X7iLIG5STKZ7dTqHNg3YPknov2yVE2upJHGR gEMd1V6fMiClv8kYncxpj25aUiJU/WfBNWtTmPfVjenjVG6CSY/BEbyJzgbKa0OrIBda a/svI04My7Xzu7wT7fnO/lqThonp65ZhQjmkClbhnNixBKWrauTQvxVx5zRWMKLXyQSP 3poQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :organization:references:in-reply-to:message-id:subject:cc:to:from :date; bh=hc5pTwn21kOvX2k3Jtpmub8LhW4Z+Wq2xio9EA2AV3U=; b=llpSQkJDRIh9Xf7ZeqP9GQgeS0T7hP1w0U66D5YLF49WqthVD3pc2dBN4uomovXibF 7GncPLeCe6cFArC/yWhSmIdxF7D+cz7BI+xGkiGzh7jgiQS7a5NM0qnA9S/Sj4NbNHPu j5VJCj0ILo6DZPgQeMscXuoDDRL63nuE1SObS9eZqUAAooW8bVKKMiqhZ/YPuDssRf94 5zzu2Z9Lra/CezzrPLV8kp6EFzaba2/PTOoqOPVIRysWyKISWKQNmqh5myqIGwUZKUAv grhPY2swFqICgJq1/9FHIpv97ZPv0JhXiaZ2bf9BR+0bDFEgR076oufHUU53hCHkbay1 fW2w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l18si14211688oth.236.2020.01.16.16.02.10; Thu, 16 Jan 2020 16:02:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2395532AbgAPSWk convert rfc822-to-8bit (ORCPT + 99 others); Thu, 16 Jan 2020 13:22:40 -0500 Received: from relay6-d.mail.gandi.net ([217.70.183.198]:35717 "EHLO relay6-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390359AbgAPSW2 (ORCPT ); Thu, 16 Jan 2020 13:22:28 -0500 X-Originating-IP: 91.224.148.103 Received: from xps13 (unknown [91.224.148.103]) (Authenticated sender: miquel.raynal@bootlin.com) by relay6-d.mail.gandi.net (Postfix) with ESMTPSA id 52FC1C0005; Thu, 16 Jan 2020 18:22:23 +0000 (UTC) Date: Thu, 16 Jan 2020 19:22:21 +0100 From: Miquel Raynal To: zdhays@gmail.com Cc: zhays@lexmark.com, Richard Weinberger , Vignesh Raghavendra , Frieder Schrempf , Boris Brezillon , Thomas Gleixner , Piotr Sroka , Marco Felsch , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] mtd: rawnand: micron: don't error out if internal ECC is set Message-ID: <20200116192221.49986c13@xps13> In-Reply-To: <20200110162503.7185-1-zdhays@gmail.com> References: <20200110162503.7185-1-zdhays@gmail.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Zak, zdhays@gmail.com wrote on Fri, 10 Jan 2020 11:25:01 -0500: > From: Zak Hays > > Recent changes to the driver require use of on-die correction if > the internal ECC enable bit is set. On some Micron parts, this bit > is enabled by default and there is no method for disabling it. > > This is a false assumption though as that bit being enabled does not > necessarily mean that the on-die ECC *has* to be used. It has been > verified with a Micron FAE that other methods of error correction are > still valid even if this bit is set. > > HW ECC offers generally higher performance than on-die so it is > preferred in some situations. This also allows multiple NAND parts to > be supported on the same PCB as some parts may not support on-die > error correction. > > With that in mind, only throw a warning that the on-die bit is set > and allow the init to continue. I don't think I can take this patch as-is. We must find a reliable way to discriminate Micron parts features. If we cannot (I think we can't before of the endless list of bugs they have introduced without documenting them), the best way is to build a static table. > > Signed-off-by: Zak Hays > --- > drivers/mtd/nand/raw/nand_micron.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c > index 56654030ec7f..ec40c76443be 100644 > --- a/drivers/mtd/nand/raw/nand_micron.c > +++ b/drivers/mtd/nand/raw/nand_micron.c > @@ -455,9 +455,7 @@ static int micron_nand_init(struct nand_chip *chip) > > if (ondie == MICRON_ON_DIE_MANDATORY && > chip->ecc.mode != NAND_ECC_ON_DIE) { > - pr_err("On-die ECC forcefully enabled, not supported\n"); > - ret = -EINVAL; > - goto err_free_manuf_data; > + pr_warn("WARNING: On-die ECC forcefully enabled, use caution with other methods\n"); > } > > if (chip->ecc.mode == NAND_ECC_ON_DIE) { Thanks, Miquèl