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Fri, 17 Jan 2020 07:44:13 +0000 From: Yash Shah To: paul.walmsley@sifive.com, palmer@dabbelt.com Cc: aou@eecs.berkeley.edu, allison@lohutok.net, alexios.zavras@intel.com, gregkh@linuxfoundation.org, tglx@linutronix.de, bp@suse.de, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com, Yash Shah Subject: [PATCH v4 2/2] riscv: Add support to determine no. of L2 cache way enabled Date: Fri, 17 Jan 2020 13:13:38 +0530 Message-Id: <1579247018-6720-3-git-send-email-yash.shah@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1579247018-6720-1-git-send-email-yash.shah@sifive.com> References: <1579247018-6720-1-git-send-email-yash.shah@sifive.com> Content-Type: text/plain X-ClientProxiedBy: BM1PR0101CA0056.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:19::18) To CH2PR13MB3368.namprd13.prod.outlook.com (2603:10b6:610:2c::26) MIME-Version: 1.0 Received: from dhananjayk-PowerEdge-R620.open-silicon.com (114.143.65.226) by BM1PR0101CA0056.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:19::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2644.19 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: GpuJ1TSqzDt53M8nYr9xWnNV7c2vPwpgB1Pf8+i75TyyU+2+08E30gTi6+KyCBMu4+xGkUId89LeowCrAxl5AaIRjQc0txijs6klhcufWK1NnxV/vsWSai6y6XvZ5Tl8qjg1HKbAsvARWjt4mhL2waGEi5LeCbkuko67z5xPbOFPmj/+6Yc2t2Tm/DRTb6QCAwjVIZn4oCI4khOHUQ2LyDDgRwGcPqP/mQ+bsEGLocFiG2k2mVipicgkv52hq374Jgi2Thy8sTg7QNmEkxrNGzCWWH6SLK2eal12DyZTOV+gye1CGuYKxv4bonM739AevJ+bKd3W0lTOoBtfzSFua/fve0Xwt1W2HhwAwErJTUlLd51GqXxmZX6YM2fszXpJ8n43A/CCAqT6Q2zBd1PLqlQJ7IwEP58J0O0uUxD68T9rldm9sn+wXE9UFvaSAHhm X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: 61429218-f104-4329-9d40-08d79b210b8f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2020 07:44:13.0489 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lDzSpSQ3hFeiZiiCP6D+CNP+2fNu0zBd9FfOrGMZs0XR6b6EWUI+J/xSkz9ErYbvl/29RU2q6Yf8JxiUOAeIuw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR13MB3765 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah Reviewed-by: Anup Patel --- drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index a506939..3fb6404 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #define SIFIVE_L2_DIRECCFIX_LOW 0x100 @@ -31,6 +33,7 @@ static void __iomem *l2_base; static int g_irq[SIFIVE_L2_MAX_ECCINTR]; +static struct riscv_cacheinfo_ops l2_cache_ops; enum { DIR_CORR = 0, @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct notifier_block *nb) } EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier); +static int l2_largest_wayenabled(void) +{ + return readl(l2_base + SIFIVE_L2_WAYENABLE); +} + +static ssize_t number_of_ways_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", l2_largest_wayenabled()); +} + +static DEVICE_ATTR_RO(number_of_ways_enabled); + +static struct attribute *priv_attrs[] = { + &dev_attr_number_of_ways_enabled.attr, + NULL, +}; + +static const struct attribute_group priv_attr_group = { + .attrs = priv_attrs, +}; + +const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf) +{ + /* We want to use private group for L2 cache only */ + if (this_leaf->level == 2) + return &priv_attr_group; + else + return NULL; +} + static irqreturn_t l2_int_handler(int irq, void *device) { unsigned int add_h, add_l; @@ -170,6 +205,9 @@ static int __init sifive_l2_init(void) l2_config_read(); + l2_cache_ops.get_priv_group = l2_get_priv_group; + riscv_set_cacheinfo_ops(&l2_cache_ops); + #ifdef CONFIG_DEBUG_FS setup_sifive_debug(); #endif -- 2.7.4