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Date:   Fri, 17 Jan 2020 15:13:47 +0000
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From:   Krzysztof Piecuch <piecuch@protonmail.com>
Reply-To: Krzysztof Piecuch <piecuch@protonmail.com>
Subject: [PATCH] x86/tsc: Add tsc_tuned_baseclk flag disabling CPUID.16h use for tsc calibration
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Changing base clock frequency directly impacts tsc hz but not CPUID.16h
values. An overclocked CPU supporting CPUID.16h and partial CPUID.15h
support will set tsc hz according to "best guess" given by CPUID.16h
relying on tsc_refine_calibration_work to give better numbers later.
tsc_refine_calibration_work will refuse to do its work when the outcome is
off the early tsc hz value by more than 1% which is certain to happen on an
overclocked system.

Fix this by adding tsc_tuned_baseclk command line parameter that makes
the kernel ignore CPUID.16h data during TSC calibration.

Signed-off-by: Krzysztof Piecuch <piecuch@protonmail.com>
---
 Documentation/admin-guide/kernel-parameters.txt | 11 +++++++++++
 arch/x86/kernel/tsc.c                           | 16 ++++++++++++++--
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio=
n/admin-guide/kernel-parameters.txt
index ade4e6ec23e0..b251169692a8 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -4905,6 +4905,17 @@
 =09=09=09interruptions from clocksource watchdog are not
 =09=09=09acceptable).

+=09tsc_tuned_baseclk=3D
+=09=09=09[X86,INTEL] Ignore data provided by CPUID.16h during
+=09=09=09early tsc calibration. Useful when changing base clock
+=09=09=09frequency (overclocking).
+=09=09=09Warning: in case your system does not provide
+=09=09=09alternatives to determine cpu speed (HPET, PIT, complete
+=09=09=09CPUID.15h support, MSR) the kernel will fail to
+=09=09=09calibrate the clocksource and local APIC.
+=09=09=09Format: <bool> (1/Y/y=3Denabled, 0/N/n=3Ddisabled)
+=09=09=09default: disabled
+
 =09tsx=3D=09=09[X86] Control Transactional Synchronization
 =09=09=09Extensions (TSX) feature in Intel processors that
 =09=09=09support TSX control.
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 7e322e2daaf5..c9b638dd8f4d 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -59,6 +59,17 @@ struct cyc2ns {

 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);

+static bool __read_mostly tsc_tuned_baseclk;
+static int __init tsc_tuned_baseclk_setup(char *buf)
+{
+=09int ret =3D strtobool(buf, &tsc_tuned_baseclk);
+
+=09if (tsc_tuned_baseclk)
+=09=09pr_warn("tsc_tuned_baseclk: This will allow your CPU to use TSC with=
 an overclocked base clock but your system will require some means of TSC c=
alibration other than CPUID 16h.");
+=09return ret;
+}
+early_param("tsc_tuned_baseclk", tsc_tuned_baseclk_setup);
+
 __always_inline void cyc2ns_read_begin(struct cyc2ns_data *data)
 {
 =09int seq, idx;
@@ -654,7 +665,8 @@ unsigned long native_calibrate_tsc(void)
 =09 * clock, but we can easily calculate it to a high degree of accuracy
 =09 * by considering the crystal ratio and the CPU speed.
 =09 */
-=09if (crystal_khz =3D=3D 0 && boot_cpu_data.cpuid_level >=3D 0x16) {
+=09if (crystal_khz =3D=3D 0 && !tsc_tuned_baseclk &&
+=09=09boot_cpu_data.cpuid_level >=3D 0x16) {
 =09=09unsigned int eax_base_mhz, ebx, ecx, edx;

 =09=09cpuid(0x16, &eax_base_mhz, &ebx, &ecx, &edx);
@@ -692,7 +704,7 @@ static unsigned long cpu_khz_from_cpuid(void)
 =09if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL)
 =09=09return 0;

-=09if (boot_cpu_data.cpuid_level < 0x16)
+=09if (boot_cpu_data.cpuid_level < 0x16 || tsc_tuned_baseclk)
 =09=09return 0;

 =09eax_base_mhz =3D ebx_max_mhz =3D ecx_bus_mhz =3D edx =3D 0;
--
2.20.1