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From:   Thomas Gleixner <tglx@linutronix.de>
To:     Ramon Fried <rfried.dev@gmail.com>
Cc:     hkallweit1@gmail.com, Bjorn Helgaas <bhelgaas@google.com>,
        maz@kernel.org, lorenzo.pieralisi@arm.com,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: MSI irqchip configured as IRQCHIP_ONESHOT_SAFE causes spurious IRQs
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Date:   Fri, 17 Jan 2020 18:11:23 +0100
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Ramon,

Ramon Fried <rfried.dev@gmail.com> writes:
> On Fri, Jan 17, 2020 at 4:38 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>> This is wrong. MSI is edge type, not level and you are really mixing up
>> the concepts here.
>>
>> The fact that the MSI block raises a level interrupt on the output side
>> has absolutely nothing to do with the type of the MSI interrupt itself.
>>
>> MSI is edge type by definition and this does not change just because
>> there is a translation unit between the MSI interrupt and the CPU
>> controller.
>>
>> The actual MSI interrupts do not even know about the existance of that
>> MSI block at all. They do not care, as all they need to know is a
>> message and an address. When an interrupt is raised in the device the
>> MSI chip associated to the device (PCI or something else) writes this
>> message to the address exactly ONCE. And this exactly ONCE defines the
>> edge nature of MSI.
>
> OK, now I understand my mistake. thanks.

:)

>> A proper designed MSI device should not send another message before the
>> interrupt handler which is associated to the device has handled the
>> interrupt at the device level.
>
> By "MSI device" you mean the MSI controller in the SOC or the endpoint
> that sends the MSI ?

The device which incorporates the MSI endpoint. 

Thanks,

        tglx