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[209.85.208.173]) by smtp.gmail.com with ESMTPSA id p15sm12680105lfo.88.2020.01.17.16.28.14 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Jan 2020 16:28:15 -0800 (PST) Received: by mail-lj1-f173.google.com with SMTP id m26so28157481ljc.13 for ; Fri, 17 Jan 2020 16:28:14 -0800 (PST) X-Received: by 2002:a2e:b054:: with SMTP id d20mr6953708ljl.190.1579307293688; Fri, 17 Jan 2020 16:28:13 -0800 (PST) MIME-Version: 1.0 References: <20200116133102.1.I9c7e72144ef639cc135ea33ef332852a6b33730f@changeid> In-Reply-To: <20200116133102.1.I9c7e72144ef639cc135ea33ef332852a6b33730f@changeid> From: Evan Green Date: Fri, 17 Jan 2020 16:27:37 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] PCI/MSI: Avoid torn updates to MSI pairs To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 16, 2020 at 1:31 PM Evan Green wrote: > > __pci_write_msi_msg() updates three registers in the device: address > high, address low, and data. On x86 systems, address low contains > CPU targeting info, and data contains the vector. The order of writes > is address, then data. > > This is problematic if an interrupt comes in after address has > been written, but before data is updated, and the SMP affinity of > the interrupt is changing. In this case, the interrupt targets the > wrong vector on the new CPU. > > This case is pretty easy to stumble into using xhci and CPU hotplugging. > Create a script that targets interrupts at a set of cores and then > offlines those cores. Put some stress on USB, and then watch xhci lose > an interrupt and die. > > Avoid this by disabling MSIs during the update. > > Signed-off-by: Evan Green Note to reviewers: I posted a v2 of this patch with some improvements here: https://lore.kernel.org/lkml/20200117162444.v2.1.I9c7e72144ef639cc135ea33ef332852a6b33730f@changeid/T/#u