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Date:   Mon, 20 Jan 2020 10:23:00 +0100
From:   Peter Zijlstra <peterz@infradead.org>
To:     kan.liang@linux.intel.com
Cc:     eranian@google.com, acme@redhat.com, mingo@kernel.org,
        mpe@ellerman.id.au, linux-kernel@vger.kernel.org, jolsa@kernel.org,
        namhyung@kernel.org, vitaly.slobodskoy@intel.com,
        pavel.gerasimov@intel.com, ak@linux.intel.com
Subject: Re: [RESEND PATCH V5 1/2] perf/core: Add new branch sample type for
 HW index of raw branch records
Message-ID: <20200120092300.GK14879@hirez.programming.kicks-ass.net>
References: <20200116155757.19624-1-kan.liang@linux.intel.com>
 <20200116155757.19624-2-kan.liang@linux.intel.com>
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On Thu, Jan 16, 2020 at 07:57:56AM -0800, kan.liang@linux.intel.com wrote:

>  struct perf_branch_stack {
>  	__u64				nr;
> +	__u64				hw_idx;
>  	struct perf_branch_entry	entries[0];
>  };

The above and below order doesn't match.

> @@ -849,7 +853,11 @@ enum perf_event_type {
>  	 *	  char                  data[size];}&& PERF_SAMPLE_RAW
>  	 *
>  	 *	{ u64                   nr;
> -	 *        { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK
> +	 *        { u64 from, to, flags } lbr[nr];
> +	 *
> +	 *        # only available if PERF_SAMPLE_BRANCH_HW_INDEX is set
> +	 *        u64			hw_idx;
> +	 *      } && PERF_SAMPLE_BRANCH_STACK

That wants to be written as:

		{ u64			nr;
		  { u64 from, to, flags; } entries[nr];
		  { u64	hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX
		} && PERF_SAMPLE_BRANCH_STACK

But the big question is; why isn't it:

		{ u64			nr;
		  { u64	hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX
		  { u64 from, to, flags; } entries[nr];
		} && PERF_SAMPLE_BRANCH_STACK

to match the struct perf_branch_stack order. Having that variable sized
entry in the middle just seems weird.

>  	 *
>  	 * 	{ u64			abi; # enum perf_sample_regs_abi
>  	 * 	  u64			regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER