Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Peng Fan <peng.fan@nxp.com>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>
CC:     "sboyd@kernel.org" <sboyd@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        Abel Vesa <abel.vesa@nxp.com>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Anson Huang <anson.huang@nxp.com>,
        Jacky Bai <ping.bai@nxp.com>,
        "l.stach@pengutronix.de" <l.stach@pengutronix.de>
Subject: Re: [PATCH V3 1/4] clk: imx: composite-8m: add
 imx8m_clk_hw_composite_core
Thread-Topic: [PATCH V3 1/4] clk: imx: composite-8m: add
 imx8m_clk_hw_composite_core
Thread-Index: AQHVzBLeomevoDMgFk6s1Cu8sUYGcA==
Date:   Mon, 20 Jan 2020 13:41:13 +0000
Message-ID: <VI1PR04MB7023C33CB9D5EEFB094BF1ADEE320@VI1PR04MB7023.eurprd04.prod.outlook.com>
References: <1579140562-8060-1-git-send-email-peng.fan@nxp.com>
 <1579140562-8060-2-git-send-email-peng.fan@nxp.com>
Accept-Language: en-US
Content-Language: en-US
received-spf: None (protection.outlook.com: nxp.com does not designate
 permitted sender hosts)
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: 3a850660-d49e-43b5-fc05-08d79dae6aec
X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Jan 2020 13:41:13.9005
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: aUVWKH1MBEPmQAexo8ScNNifvPVUQz/QpwFdlxMh4OlrkdhvEcRY1k47bZEEWDvD9hCX4LmDZdVJUDXEZ8otSg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7149
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 16.01.2020 04:15, Peng Fan wrote:=0A=
> From: Peng Fan <peng.fan@nxp.com>=0A=
> =0A=
> There are several clock slices, current composite code=0A=
> only support bus/ip clock slices, it could not support core=0A=
> slice.=0A=
> =0A=
> So introduce a new API imx8m_clk_hw_composite_core to support=0A=
> core slice. To core slice, post divider with 3 bits width and=0A=
> no pre divider. Other fields are same as bus/ip slices.=0A=
> =0A=
> Add a flag IMX_COMPOSITE_CORE for the usecase.=0A=
> =0A=
> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>=0A=
> Signed-off-by: Peng Fan <peng.fan@nxp.com>=0A=
=0A=
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>=0A=
=0A=
> ---=0A=
>   drivers/clk/imx/clk-composite-8m.c | 18 ++++++++++++++----=0A=
>   drivers/clk/imx/clk.h              | 13 +++++++++++--=0A=
>   2 files changed, 25 insertions(+), 6 deletions(-)=0A=
> =0A=
> diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-com=
posite-8m.c=0A=
> index e0f25983e80f..4174506e8bdd 100644=0A=
> --- a/drivers/clk/imx/clk-composite-8m.c=0A=
> +++ b/drivers/clk/imx/clk-composite-8m.c=0A=
> @@ -15,6 +15,7 @@=0A=
>   #define PCG_PREDIV_MAX		8=0A=
>   =0A=
>   #define PCG_DIV_SHIFT		0=0A=
> +#define PCG_CORE_DIV_WIDTH	3=0A=
>   #define PCG_DIV_WIDTH		6=0A=
>   #define PCG_DIV_MAX		64=0A=
>   =0A=
> @@ -126,6 +127,7 @@ static const struct clk_ops imx8m_clk_composite_divid=
er_ops =3D {=0A=
>   struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,=0A=
>   					const char * const *parent_names,=0A=
>   					int num_parents, void __iomem *reg,=0A=
> +					u32 composite_flags,=0A=
>   					unsigned long flags)=0A=
>   {=0A=
>   	struct clk_hw *hw =3D ERR_PTR(-ENOMEM), *mux_hw;=0A=
> @@ -133,6 +135,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const cha=
r *name,=0A=
>   	struct clk_divider *div =3D NULL;=0A=
>   	struct clk_gate *gate =3D NULL;=0A=
>   	struct clk_mux *mux =3D NULL;=0A=
> +	const struct clk_ops *divider_ops;=0A=
>   =0A=
>   	mux =3D kzalloc(sizeof(*mux), GFP_KERNEL);=0A=
>   	if (!mux)=0A=
> @@ -149,8 +152,16 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const ch=
ar *name,=0A=
>   =0A=
>   	div_hw =3D &div->hw;=0A=
>   	div->reg =3D reg;=0A=
> -	div->shift =3D PCG_PREDIV_SHIFT;=0A=
> -	div->width =3D PCG_PREDIV_WIDTH;=0A=
> +	if (composite_flags & IMX_COMPOSITE_CORE) {=0A=
> +		div->shift =3D PCG_DIV_SHIFT;=0A=
> +		div->width =3D PCG_CORE_DIV_WIDTH;=0A=
> +		divider_ops =3D &clk_divider_ops;=0A=
> +	} else {=0A=
> +		div->shift =3D PCG_PREDIV_SHIFT;=0A=
> +		div->width =3D PCG_PREDIV_WIDTH;=0A=
> +		divider_ops =3D &imx8m_clk_composite_divider_ops;=0A=
> +	}=0A=
> +=0A=
>   	div->lock =3D &imx_ccm_lock;=0A=
>   	div->flags =3D CLK_DIVIDER_ROUND_CLOSEST;=0A=
>   =0A=
> @@ -164,8 +175,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const cha=
r *name,=0A=
>   =0A=
>   	hw =3D clk_hw_register_composite(NULL, name, parent_names, num_parents=
,=0A=
>   			mux_hw, &clk_mux_ops, div_hw,=0A=
> -			&imx8m_clk_composite_divider_ops,=0A=
> -			gate_hw, &clk_gate_ops, flags);=0A=
> +			divider_ops, gate_hw, &clk_gate_ops, flags);=0A=
>   	if (IS_ERR(hw))=0A=
>   		goto fail;=0A=
>   =0A=
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h=0A=
> index b05213b91dcf..f074dd8ec42e 100644=0A=
> --- a/drivers/clk/imx/clk.h=0A=
> +++ b/drivers/clk/imx/clk.h=0A=
> @@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, con=
st char *parent_name,=0A=
>   		struct clk *div, struct clk *mux, struct clk *pll,=0A=
>   		struct clk *step);=0A=
>   =0A=
> +#define IMX_COMPOSITE_CORE	BIT(0)=0A=
> +=0A=
>   struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,=0A=
>   					    const char * const *parent_names,=0A=
>   					    int num_parents,=0A=
>   					    void __iomem *reg,=0A=
> +					    u32 composite_flags,=0A=
>   					    unsigned long flags);=0A=
>   =0A=
> +#define imx8m_clk_hw_composite_core(name, parent_names, reg)	\=0A=
> +	imx8m_clk_hw_composite_flags(name, parent_names, \=0A=
> +			ARRAY_SIZE(parent_names), reg, \=0A=
> +			IMX_COMPOSITE_CORE, \=0A=
> +			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)=0A=
> +=0A=
>   #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg,=
 \=0A=
>   				  flags) \=0A=
>   	to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \=0A=
> -				num_parents, reg, flags))=0A=
> +				num_parents, reg, 0, flags))=0A=
>   =0A=
>   #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \=0A=
>   	imx8m_clk_hw_composite_flags(name, parent_names, \=0A=
> -		ARRAY_SIZE(parent_names), reg, \=0A=
> +		ARRAY_SIZE(parent_names), reg, 0, \=0A=
>   		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)=0A=
>   =0A=
>   #define __imx8m_clk_composite(name, parent_names, reg, flags) \=0A=
> =0A=
=0A=