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From:   <Claudiu.Beznea@microchip.com>
To:     <sre@kernel.org>, <Nicolas.Ferre@microchip.com>,
        <alexandre.belloni@bootlin.com>, <Ludovic.Desroches@microchip.com>
CC:     <linux-pm@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <Claudiu.Beznea@microchip.com>
Subject: [PATCH 15/15] power: reset: at91-reset: handle nrst async for sam9x60
Thread-Topic: [PATCH 15/15] power: reset: at91-reset: handle nrst async for
 sam9x60
Thread-Index: AQHV0EINUPsFdrOD60ihk98/gadShw==
Date:   Tue, 21 Jan 2020 10:03:39 +0000
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Handle NRST asynchronously for SAM9X60 to avoid problem with fast drop of
VDDCORE on shutdown operations in the first 100 us after CPU is shutdown.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 drivers/power/reset/at91-reset.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-re=
set.c
index 537ccb180568..3ff9d93a5226 100644
--- a/drivers/power/reset/at91-reset.c
+++ b/drivers/power/reset/at91-reset.c
@@ -35,6 +35,7 @@
=20
 #define AT91_RSTC_MR	0x08		/* Reset Controller Mode Register */
 #define AT91_RSTC_URSTEN	BIT(0)		/* User Reset Enable */
+#define AT91_RSTC_URSTASYNC	BIT(2)		/* User Reset Asynchronous Control */
 #define AT91_RSTC_URSTIEN	BIT(4)		/* User Reset Interrupt Enable */
 #define AT91_RSTC_ERSTL		GENMASK(11, 8)	/* External Reset Length */
=20
@@ -228,6 +229,13 @@ static int __init at91_reset_probe(struct platform_dev=
ice *pdev)
=20
 	platform_set_drvdata(pdev, reset);
=20
+	if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc"))=
 {
+		u32 val =3D readl(reset->rstc_base + AT91_RSTC_MR);
+
+		writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val,
+		       reset->rstc_base + AT91_RSTC_MR);
+	}
+
 	ret =3D register_restart_handler(&reset->nb);
 	if (ret) {
 		clk_disable_unprepare(reset->sclk);
--=20
2.7.4