Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp3724476ybl; Tue, 21 Jan 2020 06:02:55 -0800 (PST) X-Google-Smtp-Source: APXvYqzexbHLJjszU7+3K0LnJ4ild4BUKRGK8oU2BzVrQGOdAkzHCGqxtKoh8BvUEizXBFtgq1sc X-Received: by 2002:a05:6830:4d9:: with SMTP id s25mr3670180otd.171.1579615375624; Tue, 21 Jan 2020 06:02:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1579615375; cv=none; d=google.com; s=arc-20160816; b=Ohsb9KZqpHXULzoS8kO1ZQXSwehbytg2e1Mfqh4Wp5NJ+ARIPX6VAeVVsgqrZR/Njn d+B1WcXvM15sTh/DypdOi8GvYPjEn/nh0UqljDvFZcNfHGlluluwIKMMmm3XU0RihR6c YWsFRbk4lWJQYUARgPpL9BWIeBkjiYwqE9bF+P9NDkQ9//oznZZDIZ3xQUZ6iSrpYtoh JRgvmgQiq4aKWO9A+ZFBpX4I7BxaEbbqcka8XmObCihyKHCdu3PA6tBWJG4+PaLeL3/X r5txC6gvXqdY7gEzF7rGDCntoDDnvvSY95b8XaAhVfn3yWAZj5ZUlGeVs2uyyH6sdg4a jZgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=cxfp2RHV6ITvsEjMAGUBFvbd5NpC+8d7mZ8aV1eJQE0=; b=slMF7KImEV7Aq7StJsbJgCn8ARm83Y3DqDHNAXxv0zqm0yeHdvfKBaz0ajfardPpl+ wet5PvhAUG5y6FzvRiSVlr4o8OarbXgKKZub8Wp6pe4JVY98DhAi/gKesnO21svOAypF o7/T3ThAGlBHtrVSc6vgitxLDtSQY7q1wSJf0paWUY+P7KoZmRWLMRHx98fBpw2kYG5N 4EjDUgOUcLq4QUIa8EqY+7vcuZXhLcVCKIGkXpfjtWud54WeYaUOG4m8IihovwdD5vJO r5DSYS43XaWBvYJysBLkgyKOkHsmMHe4s9PpV+EsDFj8xjsti24FosIpUSk8bxEn8mN6 zzrA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j9si21962213otq.317.2020.01.21.06.02.42; Tue, 21 Jan 2020 06:02:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729437AbgAUOBS (ORCPT + 99 others); Tue, 21 Jan 2020 09:01:18 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:9228 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729253AbgAUOBO (ORCPT ); Tue, 21 Jan 2020 09:01:14 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 40F61A60D87D0269834C; Tue, 21 Jan 2020 22:01:12 +0800 (CST) Received: from localhost.localdomain.localdomain (10.175.113.25) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Tue, 21 Jan 2020 22:01:04 +0800 From: Chen Zhou To: , , , , CC: , , , , , , Subject: [PATCH -next 14/14] drm/amdgpu: remove unnecessary conversion to bool in gfx_v9_0.c Date: Tue, 21 Jan 2020 21:55:40 +0800 Message-ID: <20200121135540.165798-15-chenzhou10@huawei.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200121135540.165798-1-chenzhou10@huawei.com> References: <20200121135540.165798-1-chenzhou10@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.175.113.25] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fixes coccicheck warning: ./drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c:4737:43-48: WARNING: conversion to bool not needed here Signed-off-by: Chen Zhou --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 2f782c3..e4744ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4672,7 +4672,7 @@ static int gfx_v9_0_set_powergating_state(void *handle, enum amd_powergating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - bool enable = (state == AMD_PG_STATE_GATE) ? true : false; + bool enable = state == AMD_PG_STATE_GATE; switch (adev->asic_type) { case CHIP_RAVEN: @@ -4734,7 +4734,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle, case CHIP_ARCTURUS: case CHIP_RENOIR: gfx_v9_0_update_gfx_clock_gating(adev, - state == AMD_CG_STATE_GATE ? true : false); + state == AMD_CG_STATE_GATE); break; default: break; -- 2.7.4