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[209.132.180.67]) by mx.google.com with ESMTP id r12si22589714otq.156.2020.01.22.01.57.45; Wed, 22 Jan 2020 01:57:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=GoKksb91; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729868AbgAVJbu (ORCPT + 99 others); Wed, 22 Jan 2020 04:31:50 -0500 Received: from mail.kernel.org ([198.145.29.99]:44022 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729841AbgAVJbn (ORCPT ); Wed, 22 Jan 2020 04:31:43 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 908BB24672; Wed, 22 Jan 2020 09:31:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579685503; bh=U01ImcXiMVQ+6F1rV4sEe5fLN+vVgVK5/h8301HQ7L4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GoKksb91vVETzBWBXOHf7B+9lknMuPITfAhCHRie3gdhQxUsMCHTGB/gBbpVpdcMc WiGmxovtskcLU1kLggY7gcU2X+gFPLPi4vbVcQB0yq/bLojelTug41Vy3FIX5rDnTX WMpA1VXf5RMxXpkiI2KwHJWyzXKMbQZz8plbghOM= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jari Ruusu , Borislav Petkov , Fenghua Yu , Luis Chamberlain , stable@kernel.org, Linus Torvalds Subject: [PATCH 4.4 41/76] Fix built-in early-load Intel microcode alignment Date: Wed, 22 Jan 2020 10:28:57 +0100 Message-Id: <20200122092756.599155530@linuxfoundation.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200122092751.587775548@linuxfoundation.org> References: <20200122092751.587775548@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jari Ruusu commit f5ae2ea6347a308cfe91f53b53682ce635497d0d upstream. Intel Software Developer's Manual, volume 3, chapter 9.11.6 says: "Note that the microcode update must be aligned on a 16-byte boundary and the size of the microcode update must be 1-KByte granular" When early-load Intel microcode is loaded from initramfs, userspace tool 'iucode_tool' has already 16-byte aligned those microcode bits in that initramfs image. Image that was created something like this: iucode_tool --write-earlyfw=FOO.cpio microcode-files... However, when early-load Intel microcode is loaded from built-in firmware BLOB using CONFIG_EXTRA_FIRMWARE= kernel config option, that 16-byte alignment is not guaranteed. Fix this by forcing all built-in firmware BLOBs to 16-byte alignment. [ If we end up having other firmware with much bigger alignment requirements, we might need to introduce some method for the firmware to specify it, this is the minimal "just increase the alignment a bit to account for this one special case" patch - Linus ] Signed-off-by: Jari Ruusu Cc: Borislav Petkov Cc: Fenghua Yu Cc: Luis Chamberlain Cc: stable@kernel.org Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- firmware/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/firmware/Makefile +++ b/firmware/Makefile @@ -156,7 +156,7 @@ quiet_cmd_fwbin = MK_FW $@ PROGBITS=$(if $(CONFIG_ARM),%,@)progbits; \ echo "/* Generated by firmware/Makefile */" > $@;\ echo " .section .rodata" >>$@;\ - echo " .p2align $${ASM_ALIGN}" >>$@;\ + echo " .p2align 4" >>$@;\ echo "_fw_$${FWSTR}_bin:" >>$@;\ echo " .incbin \"$(2)\"" >>$@;\ echo "_fw_end:" >>$@;\