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Subject: Re: [PATCH V2 0/5] Add support to defer core initialization
From:   Vidya Sagar <vidyas@nvidia.com>
To:     <kishon@ti.com>
CC:     <jingoohan1@gmail.com>, <gustavo.pimentel@synopsys.com>,
        <lorenzo.pieralisi@arm.com>, <andrew.murray@arm.com>,
        <bhelgaas@google.com>, <thierry.reding@gmail.com>,
        <Jisheng.Zhang@synaptics.com>, <jonathanh@nvidia.com>,
        <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <sagar.tv@gmail.com>
References: <20200103100736.27627-1-vidyas@nvidia.com>
 <a8678df3-141b-51ab-b0cb-5e88c6ac91b5@nvidia.com>
Message-ID: <680a58ec-5d09-3e3b-2fd6-544c32732818@nvidia.com>
Date:   Thu, 23 Jan 2020 14:54:30 +0530
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Hi Kishon,
Apologies for pinging again. Could you please review this series?

Thanks,
Vidya Sagar

On 1/11/2020 5:18 PM, Vidya Sagar wrote:
> Hi Kishon,
> Could you please review this series?
>=20
> Also, this series depends on the following change of yours
> http://patchwork.ozlabs.org/patch/1109884/
> Whats the plan to get this merged?
>=20
> Thanks,
> Vidya Sagar
>=20
> On 1/3/20 3:37 PM, Vidya Sagar wrote:
>> EPC/DesignWare core endpoint subsystems assume that the core registers=20
>> are
>> available always for SW to initialize. But, that may not be the case=20
>> always.
>> For example, Tegra194 hardware has the core running on a clock that is=20
>> derived
>> from reference clock that is coming into the endpoint system from host.
>> Hence core is made available asynchronously based on when host system=20
>> is going
>> for enumeration of devices. To accommodate this kind of hardwares,=20
>> support is
>> required to defer the core initialization until the respective=20
>> platform driver
>> informs the EPC/DWC endpoint sub-systems that the core is indeed=20
>> available for
>> initiaization. This patch series is attempting to add precisely that.
>> This series is based on Kishon's patch that adds notification mechanism
>> support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
>>
>> Vidya Sagar (5):
>> =C2=A0=C2=A0 PCI: endpoint: Add core init notifying feature
>> =C2=A0=C2=A0 PCI: dwc: Refactor core initialization code for EP mode
>> =C2=A0=C2=A0 PCI: endpoint: Add notification for core init completion
>> =C2=A0=C2=A0 PCI: dwc: Add API to notify core initialization completion
>> =C2=A0=C2=A0 PCI: pci-epf-test: Add support to defer core initialization
>>
>> =C2=A0 .../pci/controller/dwc/pcie-designware-ep.c=C2=A0=C2=A0 |=C2=A0 7=
9 +++++++-----
>> =C2=A0 drivers/pci/controller/dwc/pcie-designware.h=C2=A0 |=C2=A0 11 ++
>> =C2=A0 drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++-=
-----
>> =C2=A0 drivers/pci/endpoint/pci-epc-core.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 19 ++-
>> =C2=A0 include/linux/pci-epc.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 2 +
>> =C2=A0 include/linux/pci-epf.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 5 +
>> =C2=A0 6 files changed, 164 insertions(+), 70 deletions(-)
>>