Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp592727ybl; Thu, 23 Jan 2020 04:29:05 -0800 (PST) X-Google-Smtp-Source: APXvYqyVx8JjlNahswutR6TksR0GpuPvxime/kGzRZUbbJ7YoLNQ+YL6o6vIZ6w5vLjqHSdeZu5X X-Received: by 2002:aca:51c9:: with SMTP id f192mr10703540oib.10.1579782544964; Thu, 23 Jan 2020 04:29:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1579782544; cv=none; d=google.com; s=arc-20160816; b=kCesotJfrrep0FKY7vEZBFbWjwl5Q5AXd7WvY5xS6PVBy6BprwX4ej8Rgw3L2bOh8V wF1qBxCZFWIVFuamoRi3CItcLBCO0IHFvy78RtJZXtQby363ubHtjTQMnkHgb+QumjoU LbDP+0wCMdjHqCt7wGTnUe5jhMXQeEXj3CCcsKgaaqALrXPU5ocRnzBn7l46la6gSFoY rlXDhH37NxA+VpQGczuEvGKV1XifBcSrDn14nqzvdUkZqqWAAooDy3JQDmjjnK5+jA0M 2QS65iq+wLP1qSu9SqtCSfYZTz/UCV+4HC+s3QAccH01ZStuE35g48216lzYvKTMenIY 5P3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:organization:references:in-reply-to:date:cc:to:from :subject:message-id; bh=yknIDCbp7SRgT8jip1S4yqL/ybO1pNM6h4RRaykeFzs=; b=PsJUd1QmkQHZ0XBImLHT1OMm0qwGux+EWSbANq6aIO+YrCOm4FdrPfqXNQmAS1tUB2 j+SSNCOxEabcd+rSFhYdAO2bXEFV4Cg6uqgEXjgvOqxkSMmPxBOa0AixGDs0fX0AECon bV/o9NYx9TmpB1Zd9Q9R8PN4MYrykZF126YRRnRw4bqzQ2ULDpVW2h5oVRWIf4HP8Rkd hAkQFfPu81F6M2K6vpCfPrRlawHtggyhX+tYzfvVpraAdR1603EvTeBjuu9AIvU4dSNV jNNdOo9CW9sN4WLXV/D5rfM8/ZtABY+vahPopupwFTUcoaJzkPdvkvCF4M9bvbv9UxdC uZAA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q190si769725oic.187.2020.01.23.04.28.52; Thu, 23 Jan 2020 04:29:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726761AbgAWM1Z (ORCPT + 99 others); Thu, 23 Jan 2020 07:27:25 -0500 Received: from mga01.intel.com ([192.55.52.88]:60058 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726232AbgAWM1Y (ORCPT ); Thu, 23 Jan 2020 07:27:24 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Jan 2020 04:27:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,353,1574150400"; d="scan'208";a="220651571" Received: from wkalinsk-mobl.ger.corp.intel.com ([10.252.23.16]) by orsmga008.jf.intel.com with ESMTP; 23 Jan 2020 04:27:20 -0800 Message-ID: Subject: Re: [PATCH v2 2/2] tpm: tis: add support for MMIO TPM on SynQuacer From: Jarkko Sakkinen To: Ard Biesheuvel , linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, masahisa.kojima@linaro.org, devicetree@vger.kernel.org, linux-integrity@vger.kernel.org, peterhuewe@gmx.de, jgg@ziepe.ca Date: Thu, 23 Jan 2020 14:27:19 +0200 In-Reply-To: <20200114141647.109347-3-ardb@kernel.org> References: <20200114141647.109347-1-ardb@kernel.org> <20200114141647.109347-3-ardb@kernel.org> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.34.1-2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2020-01-14 at 15:16 +0100, Ard Biesheuvel wrote: > When fitted, the SynQuacer platform exposes its SPI TPM via a MMIO > window that is backed by the SPI command sequencer in the SPI bus > controller. This arrangement has the limitation that only byte size > accesses are supported, and so we'll need to provide a separate set > of read and write accessors that take this into account. What is SynQuacer platform? I'm also missing a resolution why tpm_tis.c is extended to handle both and not add tpm_tis_something.c instead. It does not follow the pattern we have in place (e.g. look up tpm_tis_spi.c). /Jarkko