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From:   Thomas Gleixner <tglx@linutronix.de>
To:     sean.v.kelley@linux.intel.com, Kar Hin Ong <kar.hin.ong@ni.com>,
        Bjorn Helgaas <helgaas@kernel.org>
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        "H. Peter Anvin" <hpa@zytor.com>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        Julia Cartwright <julia.cartwright@ni.com>,
        Keng Soon Cheah <keng.soon.cheah@ni.com>,
        Gratian Crisan <gratian.crisan@ni.com>,
        Peter Zijlstra <peterz@infradead.org>
Subject: Re: RE: Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system
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Date:   Thu, 23 Jan 2020 14:08:54 +0100
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Sean,

Sean V Kelley <sean.v.kelley@linux.intel.com> writes:
> I looked into it Thomas.  The issue is as you suggested early in the
> thread.  If an IRQ arrives at line N of a non-primary IO-APIC and that
> line is masked, a new IRQ is generated on the primary IO-APIC/PIC.  
>
> The BIOS setting to address this forwarding is as above Disable INTx
> Route to PCH/ICH/SouthBridge. When this bit is set, local INTx messages
> received from the PCI-E ports are not routed to legacy PCH - they are
> either converted into MSI via the integrated I/OxAPIC (if the I/OxAPIC
> mask bit is clear in the appropriate entries) or cause no further
> action (when mask bit is set).
>
> This capability is tested and supported fully on Intel platforms.

Thanks for the confirmation.

> Once you get to SKX/CLX things change and integrated IOxAPICs in the
> IIO module convert legacy PCI Express interrupt messages into MSI
> interrupts directly.  Beyond SKX/CLX there are no longer IOxAPICs in
> IIO. IOxAPIC is only in the PCH. Devices connected to the
> IIO will use native MSI/MSI-x mechanisms.
>
> The problem is with the absolute lack of useful documentation.  That’s
> not acceptable.

Yeah.

> You recall the work Olaf and Stefan did at SuSE ten years ago (?) on
> boot irq quirks and the amount of research they had to do it learn
> about the behavior.[4]

Oh yes.

> From a Real-Time Linux perspective this is really important to me.  As
> we get closer to fully mainlined we need to have this information
> readily available with greater usage of threaded irqs in combination
> with legacy interrupts on the older platforms.
>
> So I will ensure we actually create useful information pointing to this
> behavior either in kernel docs or online as in a white paper or both.

Great.

>> As we have already quirks in drivers/pci/quirks.c which handle the
>> same issue on older chipsets, we really should add one for these kind
>> of systems to avoid fiddling with the BIOS (which you can, but most
>> people cannot).

> Agreed, and I will follow-up with Kar Hin Ong to get them added.

Much appreciated.

Thanks,

        tglx