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[4.15.122.74]) by smtp.gmail.com with ESMTPSA id c18sm3702271pfr.40.2020.01.23.11.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jan 2020 11:44:16 -0800 (PST) Message-ID: <5e29f790.1c69fb81.734a2.8d5f@mx.google.com> Date: Thu, 23 Jan 2020 11:44:15 -0800 From: Paul Burton To: Jiaxun Yang CC: linux-mips@vger.kernel.org CC: chenhc@lemote.com, paul.burton@mips.com, linux-kernel@vger.kernel.org, Jiaxun Yang CC: linux-mips@vger.kernel.org Subject: Re: [PATCH 1/3] MIPS: Make DIEI support as a config option References: <20200113101501.37985-1-jiaxun.yang@flygoat.com> In-Reply-To: <20200113101501.37985-1-jiaxun.yang@flygoat.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, Jiaxun Yang wrote: > DI(Disable Interrupt) and EI(Enable Interrupt) instructions is required by > MIPSR2/MIPSR6, however, it appears to be buggy on some processors such as > Loongson-3A1000. Thus we make it as a config option to allow disable it at > compile time with CPU_MIPSR2 selected. Series applied to mips-next. > MIPS: Make DIEI support as a config option > commit ba9196d2e005 > https://git.kernel.org/mips/c/ba9196d2e005 > > Signed-off-by: Jiaxun Yang > Signed-off-by: Paul Burton > > MIPS: Loongson64: Bump ISA level to MIPSR2 > commit 51522217f65f > https://git.kernel.org/mips/c/51522217f65f > > Signed-off-by: Jiaxun Yang > Signed-off-by: Paul Burton > > MIPS: Loongson64: Disable exec hazard > commit 1306cc0a3091 > https://git.kernel.org/mips/c/1306cc0a3091 > > Signed-off-by: Jiaxun Yang > Signed-off-by: Paul Burton Thanks, Paul [ This message was auto-generated; if you believe anything is incorrect then please email paulburton@kernel.org to report it. ]