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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Peng Fan <peng.fan@nxp.com>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>
CC:     "sboyd@kernel.org" <sboyd@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        Abel Vesa <abel.vesa@nxp.com>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Anson Huang <anson.huang@nxp.com>,
        Jacky Bai <ping.bai@nxp.com>,
        "l.stach@pengutronix.de" <l.stach@pengutronix.de>
Subject: Re: [PATCH V3 2/4] clk: imx: imx8mq: use imx8m_clk_hw_composite_core
Thread-Topic: [PATCH V3 2/4] clk: imx: imx8mq: use imx8m_clk_hw_composite_core
Thread-Index: AQHVzBLhUkGtl3RwMUeoFEsar3ylZA==
Date:   Mon, 27 Jan 2020 20:33:10 +0000
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On 27.01.2020 07:00, Peng Fan wrote:=0A=
>> Subject: Re: [PATCH V3 2/4] clk: imx: imx8mq: use=0A=
>> imx8m_clk_hw_composite_core=0A=
>>=0A=
>> On 16.01.2020 04:15, Peng Fan wrote:=0A=
>>> From: Peng Fan <peng.fan@nxp.com>=0A=
>>>=0A=
>>> Use imx8m_clk_hw_composite_core to simplify code.=0A=
>>>=0A=
>>> Reviewed-by: Abel Vesa <abel.vesa@nxp.com>=0A=
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>=0A=
>>> ---=0A=
>>>    drivers/clk/imx/clk-imx8mq.c | 22 ++++++++--------------=0A=
>>>    1 file changed, 8 insertions(+), 14 deletions(-)=0A=
>>>=0A=
>>> diff --git a/drivers/clk/imx/clk-imx8mq.c=0A=
>>> b/drivers/clk/imx/clk-imx8mq.c index 4c0edca1a6d0..e928c1355ad8=0A=
>> 100644=0A=
>>> --- a/drivers/clk/imx/clk-imx8mq.c=0A=
>>> +++ b/drivers/clk/imx/clk-imx8mq.c=0A=
>>> @@ -403,22 +403,16 @@ static int imx8mq_clocks_probe(struct=0A=
>>> platform_device *pdev)=0A=
>>>=0A=
>>>    	/* CORE */=0A=
>>>    	hws[IMX8MQ_CLK_A53_SRC] =3D imx_clk_hw_mux2("arm_a53_src",=0A=
>> base + 0x8000, 24, 3, imx8mq_a53_sels, ARRAY_SIZE(imx8mq_a53_sels));=0A=
>>> -	hws[IMX8MQ_CLK_M4_SRC] =3D imx_clk_hw_mux2("arm_m4_src", base=0A=
>> + 0x8080, 24, 3, imx8mq_arm_m4_sels, ARRAY_SIZE(imx8mq_arm_m4_sels));=0A=
>>> -	hws[IMX8MQ_CLK_VPU_SRC] =3D imx_clk_hw_mux2("vpu_src", base +=0A=
>> 0x8100, 24, 3, imx8mq_vpu_sels, ARRAY_SIZE(imx8mq_vpu_sels));=0A=
>>> -	hws[IMX8MQ_CLK_GPU_CORE_SRC] =3D=0A=
>> imx_clk_hw_mux2("gpu_core_src", base + 0x8180, 24, 3,=0A=
>> imx8mq_gpu_core_sels, ARRAY_SIZE(imx8mq_gpu_core_sels));=0A=
>>> -	hws[IMX8MQ_CLK_GPU_SHADER_SRC] =3D=0A=
>> imx_clk_hw_mux2("gpu_shader_src", base + 0x8200, 24, 3,=0A=
>> imx8mq_gpu_shader_sels,  ARRAY_SIZE(imx8mq_gpu_shader_sels));=0A=
>>> -=0A=
>>>    	hws[IMX8MQ_CLK_A53_CG] =3D=0A=
>> imx_clk_hw_gate3_flags("arm_a53_cg", "arm_a53_src", base + 0x8000, 28,=
=0A=
>> CLK_IS_CRITICAL);=0A=
>>> -	hws[IMX8MQ_CLK_M4_CG] =3D imx_clk_hw_gate3("arm_m4_cg",=0A=
>> "arm_m4_src", base + 0x8080, 28);=0A=
>>> -	hws[IMX8MQ_CLK_VPU_CG] =3D imx_clk_hw_gate3("vpu_cg", "vpu_src",=0A=
>> base + 0x8100, 28);=0A=
>>> -	hws[IMX8MQ_CLK_GPU_CORE_CG] =3D imx_clk_hw_gate3("gpu_core_cg",=0A=
>> "gpu_core_src", base + 0x8180, 28);=0A=
>>> -	hws[IMX8MQ_CLK_GPU_SHADER_CG] =3D=0A=
>> imx_clk_hw_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28);=
=0A=
>>> -=0A=
>>>    	hws[IMX8MQ_CLK_A53_DIV] =3D=0A=
>> imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3);=
=0A=
>>> -	hws[IMX8MQ_CLK_M4_DIV] =3D imx_clk_hw_divider2("arm_m4_div",=0A=
>> "arm_m4_cg", base + 0x8080, 0, 3);=0A=
>>> -	hws[IMX8MQ_CLK_VPU_DIV] =3D imx_clk_hw_divider2("vpu_div",=0A=
>> "vpu_cg", base + 0x8100, 0, 3);=0A=
>>> -	hws[IMX8MQ_CLK_GPU_CORE_DIV] =3D=0A=
>> imx_clk_hw_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3);=
=0A=
>>> -	hws[IMX8MQ_CLK_GPU_SHADER_DIV] =3D=0A=
>> imx_clk_hw_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0,=
=0A=
>> 3);=0A=
>>> +=0A=
>>> +	hws[IMX8MQ_CLK_M4_DIV] =3D=0A=
>> imx8m_clk_hw_composite_core("arm_m4_div", imx8mq_arm_m4_sels, base=0A=
>> + 0x8080);=0A=
>>> +	hws[IMX8MQ_CLK_VPU_DIV] =3D=0A=
>> imx8m_clk_hw_composite_core("vpu_div", imx8mq_vpu_sels, base +=0A=
>> 0x8100);=0A=
>>> +	hws[IMX8MQ_CLK_GPU_CORE_DIV] =3D=0A=
>> imx8m_clk_hw_composite_core("gpu_core_div", imx8mq_gpu_core_sels,=0A=
>> base + 0x8180);=0A=
>>> +	hws[IMX8MQ_CLK_GPU_SHADER_DIV] =3D=0A=
>>> +imx8m_clk_hw_composite("gpu_shader_div", imx8mq_gpu_shader_sels,=0A=
>> base=0A=
>>> ++ 0x8200);=0A=
>>=0A=
>>> +	/* For DTS which still assign parents for gpu core src clk */=0A=
>>> +	hws[IMX8MQ_CLK_GPU_CORE_SRC] =3D=0A=
>> hws[IMX8MQ_CLK_GPU_CORE_DIV];=0A=
>>> +	hws[IMX8MQ_CLK_GPU_SHADER_SRC] =3D=0A=
>> hws[IMX8MQ_CLK_GPU_SHADER_DIV];=0A=
>>=0A=
>> Why not assign to all the old clocks?=0A=
> =0A=
> Are those clocks expect the GPU ones needed?=0A=
> =0A=
> Currently only the gpu clocks are needed, others are not used in dts.=0A=
> =0A=
> For dts update to use the SRC clocks should be avoided in future for Linu=
x,=0A=
> DIV clocks should be used.=0A=
> =0A=
> How do you think?=0A=
=0A=
In theory backwards compatibility should be supported at the level of =0A=
"DT bindings", not just hacked for a particular DT. In this case it's =0A=
easy to add aliases for everything, just slightly verbose.=0A=
=0A=
It might also make sense to add new defines for the composite clock so =0A=
that IMX8MQ_CLK_GPU_CORE looks like IMX8MQ_CLK_DSI_CORE and all the _SRC =
=0A=
_DIV _CG stuff is just aliases to the unsuffixed composite.=0A=
=0A=
--=0A=
Regards,=0A=
Leonard=0A=