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[209.132.180.67]) by mx.google.com with ESMTP id x5si4982158oic.72.2020.01.28.03.39.24; Tue, 28 Jan 2020 03:39:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725965AbgA1Li2 (ORCPT + 99 others); Tue, 28 Jan 2020 06:38:28 -0500 Received: from foss.arm.com ([217.140.110.172]:55540 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725903AbgA1Li1 (ORCPT ); Tue, 28 Jan 2020 06:38:27 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1B170101E; Tue, 28 Jan 2020 03:38:27 -0800 (PST) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1B5043F52E; Tue, 28 Jan 2020 03:38:26 -0800 (PST) Date: Tue, 28 Jan 2020 11:38:21 +0000 From: Sudeep Holla To: Peng Fan Cc: Etienne Carriere , "f.fainelli@gmail.com" , "andre.przywara@arm.com" , "linux-kernel@vger.kernel.org" , etienne carriere , Sudeep Holla Subject: Re: [PATCH v11 2/2] mailbox: introduce ARM SMC based mailbox Message-ID: <20200128113821.GA36168@bogus> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 27, 2020 at 12:58:12PM +0000, Peng Fan wrote: > > Subject: Re: [PATCH v11 2/2] mailbox: introduce ARM SMC based mailbox > > > > Hello Peng and all, > > > From: Peng Fan > > > > > > This mailbox driver implements a mailbox which signals transmitted > > > data via an ARM smc (secure monitor call) instruction. The mailbox > > > receiver is implemented in firmware and can synchronously return data > > > when it returns execution to the non-secure world again. > > > An asynchronous receive path is not implemented. > > > This allows the usage of a mailbox to trigger firmware actions on SoCs > > > which either don't have a separate management processor or on which > > > such a core is not available. A user of this mailbox could be the SCP > > > interface. > > > [...] > > I've successfully tested your change on my board. It is a stm32mp1 with TZ > > secure hardening and I run an OP-TEE firmware (possibly a TF-A > > sp_min) with a SCMI server for clock and reset. Upstream in progress. > > The platform uses 2 instances of your SMC based mailbox device driver > > (2 mailboxes). Works nice with your change. > > > > You can add my T-b tag: Tested-by: Etienne Carriere > > > > Thanks, but this patch has been dropped. > > Per Sudeep, we all use smc transport, not smc mailbox , > Yes, I asked if there are any other users of SMC mailbox other than SCMI. We are planning to separate the transport from the SCMI driver[1] to enable transport other than mailbox. SMC can be one of them and the other one planned is virtio. Please feel free to add to the discussion or review. -- Regards, Sudeep [1] https://lore.kernel.org/lkml/f170b33989b426ac095952634fcd1bf45b86a7a3.1580208329.git.viresh.kumar@linaro.org