Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp361664ybl; Tue, 28 Jan 2020 04:40:36 -0800 (PST) X-Google-Smtp-Source: APXvYqwnL+KnYuYw04qqYSL+SyunBZxWzmU2tQIcxSzpLMgCV2vtBYcwTIXrx/kll/ZCW8DGmta4 X-Received: by 2002:a9d:6ac2:: with SMTP id m2mr16318409otq.191.1580215236509; Tue, 28 Jan 2020 04:40:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1580215236; cv=none; d=google.com; s=arc-20160816; b=hGOv/pGbpYC+g4xmBraGL3QHJakmWm+OLLOrEshAaPBZCeNvkxpTXMHxyA657Q7UCx 0HuLZEfUhzwAaEqO0zAHI/tXVwiY28hk1J8uVdQSG/wLohIgXY0w7WA41HVUnQG87vau t4tfeSsX72uz9Woot4a2u3+TdJJhIA5EoUsszIQa851K95fBx3NzYCFeUwe0yYhZ5r0C mUUUT5BGU/YlYiwiDrAM0Xf2bNanL2g5i/3R0/feH+H9AgjGaeVEjjzOnrziBt17P1mM o+kGtSL3Oj7l7FRtiz46QuuIoxXygEksqz++aFGGlbPE9ItZUEw7Of7qiSwN1dZudeyC MJJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=cqKaUefARHs7WW22GAETszvQl18NiUKxBBjl/FN6Jig=; b=VzEZf5+KVE15GPCVODh8Iifswm0u3pFOZS18Cb96VnaRGRjt8jLAg+tAIdfJ8DKdWk zmV8aoF+nhRIhIMC8zZCkZs4NvVSGPeDGJ6KYrb+UtUi+vTUcr+Ogb8fBasMsDJJ0YyP yyVy7KSHuD30+F3TTg+y3y+erEMEQRBTA4XY2ZCLYNgYEkFZ6p9hzQTGUqf+k+wE34y4 MSUm1DhrpyXObUV13+PuVvRZkjZy/dzGb31RwcUBbizGmWX5v+GaygN9w1LCtB5DuV8D 6s6PrIay2xY/utUOOegGqxC71w0785IY34Ukh545qAyCox09aGQ2JafcyDbAX8IqTnNV 3gMQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n25si5000793oij.175.2020.01.28.04.40.24; Tue, 28 Jan 2020 04:40:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726129AbgA1Mjc (ORCPT + 99 others); Tue, 28 Jan 2020 07:39:32 -0500 Received: from foss.arm.com ([217.140.110.172]:56236 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725852AbgA1Mjc (ORCPT ); Tue, 28 Jan 2020 07:39:32 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C1BDB101E; Tue, 28 Jan 2020 04:39:31 -0800 (PST) Received: from p8cg001049571a15.arm.com (unknown [10.163.1.151]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2E8FE3F52E; Tue, 28 Jan 2020 04:39:27 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Marc Zyngier , James Morse , Suzuki K Poulose , Mark Rutland , kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org Subject: [PATCH 0/6] Introduce ID_PFR2 and other CPU feature changes Date: Tue, 28 Jan 2020 18:09:03 +0530 Message-Id: <1580215149-21492-1-git-send-email-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series is primarily motivated from an adhoc list from Mark Rutland during our ID_ISAR6 discussion [1]. Besides, it also includes a patch which does macro replacement for various open bits shift encodings in various CPU ID registers. This series is based on linux-next 20200124. [1] https://patchwork.kernel.org/patch/11287805/ Is there anything else apart from these changes which can be accommodated in this series, please do let me know. Thank you. Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: James Morse Cc: Suzuki K Poulose Cc: Mark Rutland Cc: kvmarm@lists.cs.columbia.edu Cc: linux-kernel@vger.kernel.org Anshuman Khandual (6): arm64/cpufeature: Introduce ID_PFR2 CPU register arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register arm64/cpufeature: Replace all open bits shift encodings with macros arch/arm64/include/asm/cpu.h | 1 + arch/arm64/include/asm/sysreg.h | 51 +++++++++++++++++++ arch/arm64/kernel/cpufeature.c | 87 ++++++++++++++++++++++----------- arch/arm64/kernel/cpuinfo.c | 1 + arch/arm64/kvm/sys_regs.c | 2 +- 5 files changed, 112 insertions(+), 30 deletions(-) -- 2.20.1