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From:   Thomas Gleixner <tglx@linutronix.de>
To:     christopher.s.hall@intel.com, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@redhat.com,
        x86@kernel.org, jacob.e.keller@intel.com, richardcochran@gmail.com,
        davem@davemloft.net, sean.v.kelley@intel.com
Cc:     Christopher Hall <christopher.s.hall@intel.com>
Subject: Re: [Intel PMC TGPIO Driver 0/5] Add support for Intel PMC Time GPIO Driver with PHC interface changes to support additional H/W Features
In-Reply-To: <20191211214852.26317-1-christopher.s.hall@intel.com>
References: <20191211214852.26317-1-christopher.s.hall@intel.com>
Date:   Fri, 31 Jan 2020 19:14:49 +0100
Message-ID: <87eevf4hnq.fsf@nanos.tec.linutronix.de>
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christopher.s.hall@intel.com writes:
> From: Christopher Hall <christopher.s.hall@intel.com>
>
> Upcoming Intel platforms will have Time-Aware GPIO (TGPIO) hardware.
> The TGPIO logic is driven by the Always Running Timer (ART) that's
> related to TSC using CPUID[15H] (See Intel SDM Invariant
> Time-Keeping).
>
> The ART frequency is not adjustable. In order, to implement output
> adjustments an additional edge-timestamp API is added, as well, as
> a periodic output frequency adjustment API. Togther, these implement
> equivalent functionality to the existing SYS_OFFSET_* and frequency
> adjustment APIs.
>
> The TGPIO hardware doesn't implement interrupts. For TGPIO input, the
> output edge-timestamp API is re-used to implement a user-space polling
> interface. For periodic input (e.g. PPS) this is fairly efficient,
> requiring only a marginally faster poll rate than the input event
> frequency.

I really have a hard time to understand why this is implemented as part
of PTP while you talk about PPS at the same time.

Proper information about why this approach was chosen and what that
magic device is used for would be really helpful.

Thanks,

        tglx