Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp3469678ybl; Mon, 3 Feb 2020 00:36:25 -0800 (PST) X-Google-Smtp-Source: APXvYqwOM2DgT2tboWow6bTRPlSMKUGo+n9PXAIW2Kdlmb/tG4UrmR8Z5PFv0lIdajA2ch8mM4dc X-Received: by 2002:a05:6830:10a:: with SMTP id i10mr16295039otp.365.1580718985052; Mon, 03 Feb 2020 00:36:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1580718985; cv=none; d=google.com; s=arc-20160816; b=R3bcTvf9fw/Z8OO8pceU2xNI7PAyr5Xe5x+moMj8G+Ptyla7LzFYxExdybXVEdcY1c c5EEOl+AQ6K2ehnuyCdBMgqPDlseuYyGdXY9kSOYmK+/oepo3DarsCbfzyg33vssr2nU 2HRXrVlAo/c5A4ZDdMYE6i+6y9A4NT2N9+ZLFSi6MerlCZUdCbAzi9RkSf1+2sLFEJhJ HvJcSNyVNDxia8ju+CjiyT1c4qxyxmKt9FcuihB0tnb7O2QgWiFS3U+W9udd4STA/HRB j0iE3muTdQTBZ+w9sRWMoMeiuPiXvNJN0HWCMQaylQcVmyLwwjhwfTmXzz5DMSRfyuEb KRpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:date:cc:to:subject:from:message-id :dkim-signature; bh=S1h3J5fMUjsNTF7VkXfe5cliEvJr6GtLTC9ah4vuETY=; b=QjCtRfva0d0kAY36tUvPaMudXjDL3ZD2s9qCBqZ2vFVUSuoNH0L/+nBVnAYBygckrG x8cheZ9XLZGVAHpz0vO24KFsAqOFZTugLE5BOaLE5NXw5+Wve6SVlX6dcjKiWYjFq2pb 8skf42TkQ3OO/Q5+2EuZlehvLZPbY6JhnlvH4OX7MZrV0LqdLQke1OogO6PMQl/Wp6ot YQFSjd9VT3rUlt7lHB1IA64ei1wYKD9w8W++k2xa9nuJlgvKmEVU16EdR/bqzZsmosDK pIgu/TvwVIVjVbG4psunXv2qKB3oAO2MeL+FAP5VG45Hzt1buPMJbkgXoqKiTZ/l+x45 pCsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@c-s.fr header.s=mail header.b=nNh3p4Sv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d17si7342980oij.136.2020.02.03.00.36.13; Mon, 03 Feb 2020 00:36:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@c-s.fr header.s=mail header.b=nNh3p4Sv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727234AbgBCHL7 (ORCPT + 99 others); Mon, 3 Feb 2020 02:11:59 -0500 Received: from pegase1.c-s.fr ([93.17.236.30]:15338 "EHLO pegase1.c-s.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726084AbgBCHL6 (ORCPT ); Mon, 3 Feb 2020 02:11:58 -0500 Received: from localhost (mailhub1-int [192.168.12.234]) by localhost (Postfix) with ESMTP id 489zXS1YKhz9tyK1; Mon, 3 Feb 2020 08:11:52 +0100 (CET) Authentication-Results: localhost; dkim=pass reason="1024-bit key; insecure key" header.d=c-s.fr header.i=@c-s.fr header.b=nNh3p4Sv; dkim-adsp=pass; dkim-atps=neutral X-Virus-Scanned: Debian amavisd-new at c-s.fr Received: from pegase1.c-s.fr ([192.168.12.234]) by localhost (pegase1.c-s.fr [192.168.12.234]) (amavisd-new, port 10024) with ESMTP id ej8gC9mxBZP7; Mon, 3 Feb 2020 08:11:52 +0100 (CET) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase1.c-s.fr (Postfix) with ESMTP id 489zXS0HVXz9tyK0; Mon, 3 Feb 2020 08:11:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=c-s.fr; s=mail; t=1580713912; bh=S1h3J5fMUjsNTF7VkXfe5cliEvJr6GtLTC9ah4vuETY=; h=From:Subject:To:Cc:Date:From; b=nNh3p4Sv59HLG9j+ax6EpZV716oUTerzA2khBfmmQHfbto/CNf0AeqM1Wb8TWjxwP jHCzqZ4Hl/liGrpwvI6BMPZbl+BqNif65Rpd9uBzDqcip97W3l6Zs2Nq2Cd0sooC+n Ew1N2v6ICBjX1e0E1kkl+94f253ifyGFQa3Igd8A= Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 9618D8B791; Mon, 3 Feb 2020 08:11:56 +0100 (CET) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id ZUomNni_0tTE; Mon, 3 Feb 2020 08:11:56 +0100 (CET) Received: from po14934vm.idsi0.si.c-s.fr (po15451.idsi0.si.c-s.fr [172.25.230.102]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 50D5E8B752; Mon, 3 Feb 2020 08:11:56 +0100 (CET) Received: by po14934vm.idsi0.si.c-s.fr (Postfix, from userid 0) id 8285A652AD; Mon, 3 Feb 2020 07:11:55 +0000 (UTC) Message-Id: <80ebd9075cd7c8b412c6d5d05f7542f9026642ef.1580713729.git.christophe.leroy@c-s.fr> From: Christophe Leroy Subject: [PATCH v3 1/7] powerpc/mm: Implement set_memory() routines To: Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , ruscur@russell.cc Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Date: Mon, 3 Feb 2020 07:11:55 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The set_memory_{ro/rw/nx/x}() functions are required for STRICT_MODULE_RWX, and are generally useful primitives to have. This implementation is designed to be completely generic across powerpc's many MMUs. It's possible that this could be optimised to be faster for specific MMUs, but the focus is on having a generic and safe implementation for now. This implementation does not handle cases where the caller is attempting to change the mapping of the page it is executing from, or if another CPU is concurrently using the page being altered. These cases likely shouldn't happen, but a more complex implementation with MMU-specific code could safely handle them, so that is left as a TODO for now. Signed-off-by: Russell Currey Signed-off-by: Christophe Leroy --- v3: - Changes 'action' from int to long to avoid build failure on PPC64 when casting to/from void* - Move pageattr.o into obj-y in Makefile v2: - use integers instead of pointers for action - drop action check, nobody should call change_memory_attr() directly. Should it happen, the function will just do nothing. - Renamed confusing 'pte_val' var to 'pte' as pte_val() is already a function. Signed-off-by: Christophe Leroy --- arch/powerpc/Kconfig | 1 + arch/powerpc/include/asm/set_memory.h | 32 ++++++++++++ arch/powerpc/mm/Makefile | 2 +- arch/powerpc/mm/pageattr.c | 74 +++++++++++++++++++++++++++ 4 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/include/asm/set_memory.h create mode 100644 arch/powerpc/mm/pageattr.c diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 730c06668f22..d0c6e7b7a62d 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -129,6 +129,7 @@ config PPC select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_MEMBARRIER_CALLBACKS select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64 + select ARCH_HAS_SET_MEMORY select ARCH_HAS_STRICT_KERNEL_RWX if ((PPC_BOOK3S_64 || PPC32) && !HIBERNATION) select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UACCESS_FLUSHCACHE diff --git a/arch/powerpc/include/asm/set_memory.h b/arch/powerpc/include/asm/set_memory.h new file mode 100644 index 000000000000..64011ea444b4 --- /dev/null +++ b/arch/powerpc/include/asm/set_memory.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_POWERPC_SET_MEMORY_H +#define _ASM_POWERPC_SET_MEMORY_H + +#define SET_MEMORY_RO 0 +#define SET_MEMORY_RW 1 +#define SET_MEMORY_NX 2 +#define SET_MEMORY_X 3 + +int change_memory_attr(unsigned long addr, int numpages, long action); + +static inline int set_memory_ro(unsigned long addr, int numpages) +{ + return change_memory_attr(addr, numpages, SET_MEMORY_RO); +} + +static inline int set_memory_rw(unsigned long addr, int numpages) +{ + return change_memory_attr(addr, numpages, SET_MEMORY_RW); +} + +static inline int set_memory_nx(unsigned long addr, int numpages) +{ + return change_memory_attr(addr, numpages, SET_MEMORY_NX); +} + +static inline int set_memory_x(unsigned long addr, int numpages) +{ + return change_memory_attr(addr, numpages, SET_MEMORY_X); +} + +#endif diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index 5e147986400d..a998fdac52f9 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -5,7 +5,7 @@ ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC) -obj-y := fault.o mem.o pgtable.o mmap.o \ +obj-y := fault.o mem.o pgtable.o mmap.o pageattr.o \ init_$(BITS).o pgtable_$(BITS).o \ pgtable-frag.o ioremap.o ioremap_$(BITS).o \ init-common.o mmu_context.o drmem.o diff --git a/arch/powerpc/mm/pageattr.c b/arch/powerpc/mm/pageattr.c new file mode 100644 index 000000000000..2b573768a7f7 --- /dev/null +++ b/arch/powerpc/mm/pageattr.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * MMU-generic set_memory implementation for powerpc + * + * Copyright 2019, IBM Corporation. + */ + +#include +#include + +#include +#include +#include + + +/* + * Updates the attributes of a page in three steps: + * + * 1. invalidate the page table entry + * 2. flush the TLB + * 3. install the new entry with the updated attributes + * + * This is unsafe if the caller is attempting to change the mapping of the + * page it is executing from, or if another CPU is concurrently using the + * page being altered. + * + * TODO make the implementation resistant to this. + */ +static int change_page_attr(pte_t *ptep, unsigned long addr, void *data) +{ + long action = (long)data; + pte_t pte; + + spin_lock(&init_mm.page_table_lock); + + /* invalidate the PTE so it's safe to modify */ + pte = ptep_get_and_clear(&init_mm, addr, ptep); + flush_tlb_kernel_range(addr, addr + PAGE_SIZE); + + /* modify the PTE bits as desired, then apply */ + switch (action) { + case SET_MEMORY_RO: + pte = pte_wrprotect(pte); + break; + case SET_MEMORY_RW: + pte = pte_mkwrite(pte); + break; + case SET_MEMORY_NX: + pte = pte_exprotect(pte); + break; + case SET_MEMORY_X: + pte = pte_mkexec(pte); + break; + default: + break; + } + + set_pte_at(&init_mm, addr, ptep, pte); + spin_unlock(&init_mm.page_table_lock); + + return 0; +} + +int change_memory_attr(unsigned long addr, int numpages, long action) +{ + unsigned long start = ALIGN_DOWN(addr, PAGE_SIZE); + unsigned long sz = numpages * PAGE_SIZE; + + if (!numpages) + return 0; + + return apply_to_page_range(&init_mm, start, sz, change_page_attr, (void *)action); +} -- 2.25.0