Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp4861756ybl; Tue, 4 Feb 2020 03:22:21 -0800 (PST) X-Google-Smtp-Source: APXvYqyNrOBMFQ+KvDje/1zqDmFVlckedCZVsRmJrds082uqNEqZ8m5RY/44vIfrWCmIxoEdMljG X-Received: by 2002:a05:6808:a9c:: with SMTP id q28mr3156093oij.176.1580815341222; Tue, 04 Feb 2020 03:22:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1580815341; cv=none; d=google.com; s=arc-20160816; b=ndFDsR8sbb/Wm8hiwsUmZtBCwOqmZ5+Pd9g2c9Z7XSA5UcdauR7L057HVly9FcVg+E wMdWYFiCH/7zYUv/G0yWMv9IoENucHCKoLUoxVfrA4OyZIhXdPcS6wCjTeC/cAPEPjfD 9nJxY1ti7nPrPQmFY0nyP6GYkkmN38YUD3ubxPMR4DqhrNmbb1x3nq1ywl3j683e5cGr f0EYaWWWVKIUiAj1dmVSNZ45p3rTGgu9IvaDOAvIkZQXe8J/GO65rfkO70Zhn2mMdsg4 +rL36VtUVbLHHwQyhfFgo1sLjrJCorFjzzCUzOhgwkRrCJc4Kc42AwF17059h7bY7Ljk F4Gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=ddexJiymOJOkm6mOcuFH3qQ8/CVzSV1cFWStnmWV+fo=; b=uF1rlyZm5GPbWj/KI0n1c8Km3AIv0OD15pxmUQoEY0zjNzmK2v3rMQpJKmODXurgGB jdL+ckvh9JtksOdLkQ6tO139wuJobIRZdED6NejhblZDDzXHEM8oSxBPrFPWus/0a6F7 J7DIYQI8WAtjXmq5FkSztyAWzLi44scaGUlgudb8PtyNasJ8W6qid8hxR7YEWyi4LuYt TOC9+4Z27WLMDT4G4JaFYqKd4XYEswtwZUz/aU7kH5EtuZaPY2177h2p7BEC+NHE+blH 9WtsW0vQ8Q/bfjbY7TgV02Aetz1R1sIH5wyjZLZ0lvaigbCenXuOmWrvtDi5XtD9OD3u lZHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=LkbJ4FWM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q19si11633405otm.221.2020.02.04.03.22.09; Tue, 04 Feb 2020 03:22:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=LkbJ4FWM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727578AbgBDLT7 (ORCPT + 99 others); Tue, 4 Feb 2020 06:19:59 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:19279 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727154AbgBDLT5 (ORCPT ); Tue, 4 Feb 2020 06:19:57 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Feb 2020 03:19:33 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Feb 2020 03:19:56 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Feb 2020 03:19:56 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 4 Feb 2020 11:19:56 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 4 Feb 2020 11:19:56 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 04 Feb 2020 03:19:55 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V4 17/19] arm64: tegra: Add xudc node for Tegra186 Date: Tue, 4 Feb 2020 16:47:03 +0530 Message-ID: <1580815025-10915-18-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580815025-10915-1-git-send-email-nkristam@nvidia.com> References: <1580815025-10915-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1580815173; bh=ddexJiymOJOkm6mOcuFH3qQ8/CVzSV1cFWStnmWV+fo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=LkbJ4FWM3hdm54skgvSOK2/ult4Xc/MlsuYbKgmURfiotL/dWwmDsmiOouOWVLyRf 4dA7ZeOvwImMwoYnz5o6axlt+NKO8ZT3VnXsF85uKJonmmRomBKx9ZZsJtqWKKNjnL ghzghKTTCAgS8EItedWvTHOLtEz/fw2AShsnx91CkFnE16rZ1z4/Iiuiq5Wt1OyekW vSwbEdM6ruF/lymr9Ys7ktgsTuquD1OiDeIBPjiNRBOpJt1HsdblOqxXW2dYBgId+i ZG3GG/l0jHb3XVik4nW5P9CK/2wmFbtq8zCCMaIiESq6gyR2uZwvX7JVvyzVv5yKPI xXGhDBhV9Rp2g== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra186 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT entry for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam --- V2-V4: - No changes in this version --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index c905527..58100fb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -572,6 +572,25 @@ nvidia,xusb-padctl = <&padctl>; }; + usb@3550000 { + compatible = "nvidia,tegra186-xudc"; + reg = <0x0 0x03550000 0x0 0x8000>, + <0x0 0x03558000 0x0 0x1000>; + reg-names = "base", "fpci"; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA186_CLK_XUSB_SS>, + <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA186_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + iommus = <&smmu TEGRA186_SID_XUSB_DEV>; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&padctl>; + status = "disabled"; + }; + fuse@3820000 { compatible = "nvidia,tegra186-efuse"; reg = <0x0 0x03820000 0x0 0x10000>; -- 2.7.4