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Subject: Re: [PATCH v8 2/2] spi: cadence-quadpsi: Add support for the Cadence
 QSPI controller
To:     "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@linux.intel.com>,
        Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
        Tien-Fong Chee <tien.fong.chee@intel.com>,
        Marek Vasut <marex@denx.de>
Cc:     Mark Brown <broonie@kernel.org>, Vignesh R <vigneshr@ti.com>,
        linux-spi@vger.kernel.org,
        linux-kernel <linux-kernel@vger.kernel.org>,
        Rob Herring <robh+dt@kernel.org>, dan.carpenter@oracle.com,
        cheol.yong.kim@intel.com, qi-ming.wu@intel.com
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From:   Dinh Nguyen <dinguyen@kernel.org>
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Message-ID: <d938fcc6-3e9b-2b5d-bf6c-1de7c8649798@kernel.org>
Date:   Tue, 4 Feb 2020 09:57:40 -0600
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Hi

On 1/29/20 9:41 PM, Ramuthevar, Vadivel MuruganX wrote:
> Hi Simon,
> 
> On 29/1/2020 8:01 PM, Simon Goldschmidt wrote:
>> + some people possibly interested in this for the Altera platforms
>> (see below)
>>
>> Hi all,
>>
>> This is about moving the cadence qspi driver (which is used on TI,
>> Altera FPGAs
>> and a new Intel SoC) to spi-mem.Vadivel asked me to include some
>> Altera people
>> in the loop (see below), as this is the only platform currently untested,
>> I think.
>>
>> Right now, I'm not in the position to test this myself as we're
>> currently stuck
>> on an older RT kernel, so I cannot test with HEAD.
>>
>> Feel free to involve other Intel/Altera if you're interested in that
>> peripheral
>> not being broke for socfpga in one of the next releases :-)
>>
>> On Wed, Jan 29, 2020 at 10:18 AM Ramuthevar, Vadivel MuruganX
>> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>>> Hi,
>>>
>>>    Thank you for the query and confirmation.
>>>
>>> On 29/1/2020 4:31 PM, Simon Goldschmidt wrote:
>>>
>>> On Wed, Jan 29, 2020 at 8:25 AM Ramuthevar,Vadivel MuruganX
>>> <vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
>>>
>>> From: Ramuthevar Vadivel Murugan
>>> <vadivel.muruganx.ramuthevar@linux.intel.com>
>>>
>>> Add support for the Cadence QSPI controller. This controller is
>>> present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs.
>>> This driver has been tested on the Intel LGM SoCs.
>>>
>>> So it has been tested on LGM and Vignesh gave his ok for TI. Is there
>>> anyone
>>> in the loop by now checking that this is valid for the 3rd platform
>>> using this
>>> (Altera)?
>>>
>>> Or am I wrong in thinking that this driver is meant to replace
>>> drivers/mtd/spi-nor/cadence-quadspi.c used on that platform?
>>>
>>> Absolutely , You are right, this driver is meant to replace to
>>> drivers/mtd/spi-nor/cadence-quadspi.c
>>> for Intel, TI and Altera SoC's using Cadence-QSPI IP.
>>>
>>> Meanwhile we have adapted to spi-mem framework (to support
>>> spi-nor/nand)and also didn't change the existing
>>> functionalities of spi-nor flash operations like
>>> hw_init/read/write/erase in drivers/mtd/spi-nor/cadence-quadspi.c,
>>> so it works fine (might be in Altera as well).
>>>
>>> Already I checked that Graham Moore <grmoore@opensource.altera.com>
>>> who has submitted the existing driver patches to upstream,
>>> His mail-id is bouncing back, then I decided that you are the right
>>> person to ask, could you please add them in loop if you know the team
>>> (socfpga platform engineers).

Thanks for including Graham, but he's moved on to a different career
that no longer includes Linux.

>> OK, done that. I mainly know them from U-Boot development, so I'm not
>> sure
>> who's responsible for the Linux drivers...
> Thank you for adding the team and respective members, let's see.
> 

I don't have the original patch series, but will monitor going forward.
As long as the new driver does not break legacy SoCFPGA products that
use the cadence-quadspi driver then it should be ok.

Dinh