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}; =20 + smmu: iommu@51400000 { + compatible =3D "arm,mmu-500"; + interrupt-parent =3D <&gic>; + reg =3D <0 0x51400000 0 0x40000>; + #global-interrupts =3D <1>; + #iommu-cells =3D <2>; + interrupts =3D <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D , /* Physical Secure */ --=20 2.17.1