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From:   Andy Lutomirski <luto@amacapital.net>
Mime-Version: 1.0 (1.0)
Subject: Re: [PATCH] x86/split_lock: Avoid runtime reads of the TEST_CTRL MSR
Date:   Thu, 6 Feb 2020 11:37:04 -0800
Message-Id: <6735A646-3817-4030-B9B9-11492BB1B8F0@amacapital.net>
References: <20200206164614.GA20622@agluck-desk2.amr.corp.intel.com>
Cc:     Andy Lutomirski <luto@kernel.org>,
        Sean Christopherson <sean.j.christopherson@intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Mark D Rustad <mrustad@gmail.com>,
        Arvind Sankar <nivedita@alum.mit.edu>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@kernel.org>,
        "Yu, Fenghua" <fenghua.yu@intel.com>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        H Peter Anvin <hpa@zytor.com>,
        "Raj, Ashok" <ashok.raj@intel.com>,
        "Shankar, Ravi V" <ravi.v.shankar@intel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        x86 <x86@kernel.org>, Xiaoyao Li <xiaoyao.li@intel.com>
In-Reply-To: <20200206164614.GA20622@agluck-desk2.amr.corp.intel.com>
To:     "Luck, Tony" <tony.luck@intel.com>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk


> On Feb 6, 2020, at 8:46 AM, Luck, Tony <tony.luck@intel.com> wrote:
>=20
> =EF=BB=BFOn Wed, Feb 05, 2020 at 05:18:23PM -0800, Andy Lutomirski wrote:
>>> On Wed, Feb 5, 2020 at 4:49 PM Luck, Tony <tony.luck@intel.com> wrote:
>>>=20
>>> In a context switch from a task that is detecting split locks
>>> to one that is not (or vice versa) we need to update the TEST_CTRL
>>> MSR. Currently this is done with the common sequence:
>>>        read the MSR
>>>        flip the bit
>>>        write the MSR
>>> in order to avoid changing the value of any reserved bits in the MSR.
>>>=20
>>> Cache the value of the TEST_CTRL MSR when we read it during initializati=
on
>>> so we can avoid an expensive RDMSR instruction during context switch.
>>=20
>> If something else that is per-cpu-ish gets added to the MSR in the
>> future, I will personally make fun of you for not making this percpu.
>=20
> Xiaoyao Li has posted a version using a percpu cache value:
>=20
> https://lore.kernel.org/r/20200206070412.17400-4-xiaoyao.li@intel.com
>=20
> So take that if it makes you happier.  My patch only used the
> cached value to store the state of the reserved bits in the MSR
> and assumed those are the same for all cores.
>=20
> Xiaoyao Li's version updates with what was most recently written
> on each thread (but doesn't, and can't, make use of that because we
> know that the other thread on the core may have changed the actual
> value in the MSR).
>=20
> If more bits are implemented that need to be set at run time, we
> are likely up the proverbial creek. I'll see if I can find out if
> there are plans for that.
>=20

I suppose that this whole thing is a giant mess, especially since at least o=
ne bit there is per-physical-core. Sigh.

So I don=E2=80=99t have a strong preference.=