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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id y25sm3999524oto.27.2020.02.09.17.43.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2020 17:43:42 -0800 (PST) Date: Sun, 9 Feb 2020 17:43:40 -0800 From: Kees Cook To: Peter Zijlstra Cc: Andy Lutomirski , Kristen Carlson Accardi , tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, arjan@linux.intel.com, rick.p.edgecombe@intel.com, x86@kernel.org, linux-kernel@vger.kernel.org, kernel-hardening@lists.openwall.com Subject: Re: [RFC PATCH 06/11] x86: make sure _etext includes function sections Message-ID: <202002091742.7B1E6BF19@keescook> References: <75f0bd0365857ba4442ee69016b63764a8d2ad68.camel@linux.intel.com> <20200207092423.GC14914@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20200207092423.GC14914@hirez.programming.kicks-ass.net> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 07, 2020 at 10:24:23AM +0100, Peter Zijlstra wrote: > On Thu, Feb 06, 2020 at 12:02:36PM -0800, Andy Lutomirski wrote: > > Also, in the shiny new era of > > Intel-CPUs-can’t-handle-Jcc-spanning-a-cacheline, function alignment > > may actually matter. > > *groan*, indeed. I just went and looked that up. I missed this one in > all the other fuss :/ > > So per: > > https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf > > the toolchain mitigations only work if the offset in the ifetch window > (32 bytes) is preserved. Which seems to suggest we ought to align all > functions to 32byte before randomizing it, otherwise we're almost > guaranteed to change this offset by the act of randomizing. Wheee! This sounds like in needs to be fixed generally, yes? (And I see "FUNCTION_ALIGN" macro is currently 16 bytes... -- Kees Cook