Received: by 2002:a25:1506:0:0:0:0:0 with SMTP id 6csp3980672ybv; Mon, 10 Feb 2020 09:59:54 -0800 (PST) X-Google-Smtp-Source: APXvYqzzXqAkzLArzVhCC47OgKWW/49YzemW2ufhP4ZlVRQLX8lLbzz+KcrshGJN1Zc8799/Mh1q X-Received: by 2002:a05:6808:b15:: with SMTP id s21mr144451oij.123.1581357594800; Mon, 10 Feb 2020 09:59:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581357594; cv=none; d=google.com; s=arc-20160816; b=TbgWf2e35nP6X/DahF4aD05Y8efNmDvzFcCtqthXq+anLZwKBfOFvpz1xfXLQ+ft+/ JmzffRb7MuIcWJ6EqM9vYAJrMgfUm9Y/P9yPhTHN4BRvQJbuxRlJ1agh4K3h7xgi9Dlu 8JIbuu+qyOY63GEA0RI6jT4KpF+CbaU/6CQ+xRPU1ddUBEAHaqO0FMs4wQM3J0TbdZgv 3B8Py2LzMfkX1hOV0UmqjlqJ/wZj112I4dFi5vSTwyfNo54E/rwjvmnmwIBV4lE012UH xAyKdHosWlvw5dU+zH5rvYwc33lcYOSPrSnfDoFlIfIOWwBYyEogNu4VerxtZBT8Pa4l 1ssA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:to:cc:in-reply-to:subject:from:date:dkim-signature; bh=pCOOvs7wgP9Kvj4DJOrAWEYZ2o8fXqpYVG+BiTgHmVc=; b=qN+NEco1XMRhJWA6Vvv9szvSKjaSSXevJ73d+MqB0y+k5oxJpQrlX7r+H0JpEz+kyC RyTol0BDVZ7UpZWHE4FIezdQf6h0GA42hALnrPxXeVaUxyfYPdPoWAeq3W9HOY54fbu4 dbWaLMBt+4Ix+o9o5KRjRZaZesOd2gpcPPyyYPdEbJK4ijfIBzg+QKxMmALyayCStQjf VMArl+zm/yLZfbD98CormUNmy3VJVrOlp+OB1tJFDXlUYYikvjxbYy3LS7cjSVMccXiv 8uxwwc5wBYxKAtc2e2XO5kcI1UB8zcwYl2ZIbxvmhE3Ud/8OF6uSzcK559d/i/iuKUn9 YzTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=tHwli6sF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q17si538540otk.321.2020.02.10.09.59.42; Mon, 10 Feb 2020 09:59:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=tHwli6sF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727433AbgBJR7c (ORCPT + 99 others); Mon, 10 Feb 2020 12:59:32 -0500 Received: from mail-pl1-f194.google.com ([209.85.214.194]:33743 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726950AbgBJR7b (ORCPT ); Mon, 10 Feb 2020 12:59:31 -0500 Received: by mail-pl1-f194.google.com with SMTP id ay11so3133084plb.0 for ; Mon, 10 Feb 2020 09:59:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:from:subject:in-reply-to:cc:to:message-id:mime-version :content-transfer-encoding; bh=pCOOvs7wgP9Kvj4DJOrAWEYZ2o8fXqpYVG+BiTgHmVc=; b=tHwli6sFHuojuCLon0/ryBewWROo+uN/yAbgmkGqIZJwRPwdmOdkYmng+ZvxsWshbl l6w0lKjgiDnA/24zxy5knJ7PId2iOUUUUEmLt0CbOBZ2/wuBqK/KLXjqgbQavyCPNoKL VkBPLORv4g4y6amBeTKwSxSkgTLGMS5gfvwcIH1PD0nVXmVg2CP/y3EpeMzGpv8nKjDA AIYFitsGZqHcHUQtcAjGvONsQu04Fre4sYAZQTK3B+h95lcT0GJSBrSxv+0thd/OKw7+ xDnKk4C0Msz914E775JW3VP4y2f3cWfZgMUyWySGjAcY+NWRNiN7yBxVNxasWwN0sK2D RYYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:subject:in-reply-to:cc:to:message-id :mime-version:content-transfer-encoding; bh=pCOOvs7wgP9Kvj4DJOrAWEYZ2o8fXqpYVG+BiTgHmVc=; b=XNcK6PHHmJTrK1x5JsPt/A/e0+fYUzSuDMOrLvgW3y+jRJPbJdMns+g8OCvH1whpfV 0I35hTaEUAJ4ny1n8PP4s2ixMpzMbkENpxJihSpUKQHdteL9qxLU9orUD/WARC8uPc5N 7AoEuSE8rKpRGxWiG4fXjPzSxOt5UpJ75WduSqwSXc7szuYXarxetBhgdT5OHCf+nHwr OgHFVW1ee+zvNrdRDjKgKc5VuNrqhel+mwsopOmBga4XqZdZsWoP/uAZT6EehFRlrG+H trNqHUk7vuhOG8Sn6ewrRtiTNGbF/fHHEfRsPinE4VfNRRkfANG0UgvJ37zD2T6q4Uah wjMw== X-Gm-Message-State: APjAAAXNeQJbGbWDImgq6UqvWW8QM2UXvHl8LYwwTG2Yybu2LopYyi1k zGF6FLjlo8I4/9AqfA/eRF+Cmw== X-Received: by 2002:a17:90a:fb45:: with SMTP id iq5mr237107pjb.93.1581357570204; Mon, 10 Feb 2020 09:59:30 -0800 (PST) Received: from localhost (pat_11.qualcomm.com. [192.35.156.11]) by smtp.gmail.com with ESMTPSA id g13sm979000pfo.169.2020.02.10.09.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2020 09:59:28 -0800 (PST) Date: Mon, 10 Feb 2020 09:59:28 -0800 (PST) X-Google-Original-Date: Mon, 10 Feb 2020 06:57:59 PST (-0800) From: Palmer Dabbelt X-Google-Original-From: Palmer Dabbelt Subject: Re: [PATCH] gpio/sifive: fix static checker warning In-Reply-To: <1580189061-14091-1-git-send-email-yash.shah@sifive.com> CC: linus.walleij@linaro.org, bgolaszewski@baylibre.com, Paul Walmsley , Atish Patra , wesley@sifive.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, yash.shah@sifive.com, sachin.ghadi@sifive.com, Mark Zyngier , linux-riscv@lists.infradead.org To: yash.shah@sifive.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 27 Jan 2020 21:24:21 PST (-0800), yash.shah@sifive.com wrote: > Typcasting "irq_state" leads to the below static checker warning: > The fix is to declare "irq_state" as unsigned long instead of u32. > > drivers/gpio/gpio-sifive.c:97 sifive_gpio_irq_enable() > warn: passing casted pointer '&chip->irq_state' to > 'assign_bit()' 32 vs 64. > > Fixes: 96868dce644d ("gpio/sifive: Add GPIO driver for SiFive SoCs") > Reported-by: Dan Carpenter > Signed-off-by: Yash Shah > --- > drivers/gpio/gpio-sifive.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c > index 147a1bd..c54dd08 100644 > --- a/drivers/gpio/gpio-sifive.c > +++ b/drivers/gpio/gpio-sifive.c > @@ -35,7 +35,7 @@ struct sifive_gpio { > void __iomem *base; > struct gpio_chip gc; > struct regmap *regs; > - u32 irq_state; > + unsigned long irq_state; > unsigned int trigger[SIFIVE_GPIO_MAX]; > unsigned int irq_parent[SIFIVE_GPIO_MAX]; > }; > @@ -94,7 +94,7 @@ static void sifive_gpio_irq_enable(struct irq_data *d) > spin_unlock_irqrestore(&gc->bgpio_lock, flags); > > /* Enable interrupts */ > - assign_bit(offset, (unsigned long *)&chip->irq_state, 1); > + assign_bit(offset, &chip->irq_state, 1); > sifive_gpio_set_ie(chip, offset); > } > > @@ -104,7 +104,7 @@ static void sifive_gpio_irq_disable(struct irq_data *d) > struct sifive_gpio *chip = gpiochip_get_data(gc); > int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX; > > - assign_bit(offset, (unsigned long *)&chip->irq_state, 0); > + assign_bit(offset, &chip->irq_state, 0); > sifive_gpio_set_ie(chip, offset); > irq_chip_disable_parent(d); > } Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt I'm assuming this is going to go in via some other tree (as I don't even have gpio-sifive.c yet), but LMK if you want it via the RISC-V tree. Thanks!