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Date:   Wed, 12 Feb 2020 11:42:20 +0900
From:   Kyungmin Seo <kyungmin.seo@intel.com>
To:     ulf.hansson@linaro.org, kyungmin.seo@intel.com
Cc:     linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] mmc: mmc: Fix the timing for clock changing in mmc
Message-ID: <20200212024220.GA32111@seokyung-mobl1>
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The clock has to be changed after sending CMD6 for HS mode selection in
mmc_hs400_to_hs200() function.

The JEDEC 5.0 and 5.1 said that "High-speed" mode selection has to
enable the the high speed mode timing in the Device, before chaning the
clock frequency to a frequency between 26MHz and 52MHz.

Signed-off-by: Kyungmin Seo <kyungmin.seo@intel.com>
---
 drivers/mmc/core/mmc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 3486bc7fbb64..98640b51c73e 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1196,10 +1196,6 @@ int mmc_hs400_to_hs200(struct mmc_card *card)
 	int err;
 	u8 val;
 
-	/* Reduce frequency to HS */
-	max_dtr = card->ext_csd.hs_max_dtr;
-	mmc_set_clock(host, max_dtr);
-
 	/* Switch HS400 to HS DDR */
 	val = EXT_CSD_TIMING_HS;
 	err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
@@ -1210,6 +1206,10 @@ int mmc_hs400_to_hs200(struct mmc_card *card)
 
 	mmc_set_timing(host, MMC_TIMING_MMC_DDR52);
 
+	/* Reduce frequency to HS */
+	max_dtr = card->ext_csd.hs_max_dtr;
+	mmc_set_clock(host, max_dtr);
+
 	err = mmc_switch_status(card);
 	if (err)
 		goto out_err;
-- 
2.17.1