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Date:   Wed, 12 Feb 2020 21:43:12 +0800
From:   Shawn Guo <shawnguo@kernel.org>
To:     Peng Fan <peng.fan@nxp.com>
Cc:     "sboyd@kernel.org" <sboyd@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        Abel Vesa <abel.vesa@nxp.com>,
        Leonard Crestez <leonard.crestez@nxp.com>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Anson Huang <anson.huang@nxp.com>,
        Jacky Bai <ping.bai@nxp.com>,
        "l.stach@pengutronix.de" <l.stach@pengutronix.de>
Subject: Re: [PATCH V2 1/4] clk: imx: imx8mq: fix a53 cpu clock
Message-ID: <20200212134310.GG11096@dragon>
References: <1578986576-6168-1-git-send-email-peng.fan@nxp.com>
 <1578986576-6168-2-git-send-email-peng.fan@nxp.com>
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On Tue, Jan 14, 2020 at 07:27:15AM +0000, Peng Fan wrote:
> From: Peng Fan <peng.fan@nxp.com>

The 'imx: ' in subject is not really needed.  'clk: imx8mq: ' should be
already clear enough.

> 
> The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root
> signoff timing is 1Ghz,

Is this restriction mentioned in any document? 

> however the A53 core which sources from CCM
> root could run above 1GHz which voilates the CCM.

s/voilates/violates

> 
> There is a CORE_SEL slice before A53 core, we need configure the

s/need/need to

> CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
> 
> The A53 CCM clk root should only be used when need to change ARM PLL
> frequency.
> 
> Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
> Configure a53 ccm root sources from 800MHz sys pll
> Configure a53 core sources from arm_pll_out
> Mark arm_a53_core as critical clock
> 
> Fixes: db27e40b27f1 ("clk: imx8mq: Add the missing ARM clock")

We have been running this for quite a while with OPPs above 1GHz.  Why
didn't we hear any issue report?

Shawn

> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> 
> V2:
>  None
> 
>  drivers/clk/imx/clk-imx8mq.c             | 16 ++++++++++++----
>  include/dt-bindings/clock/imx8mq-clock.h |  4 +++-
>  2 files changed, 15 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index b031183ff427..82a16b8e98a9 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -41,6 +41,8 @@ static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", };
>  static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
>  					"sys1_pll_800m", "sys1_pll_400m", "audio_pll1_out", "sys3_pll_out", };
>  
> +static const char * const imx8mq_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
> +
>  static const char * const imx8mq_arm_m4_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_250m", "sys1_pll_266m",
>  					"sys1_pll_800m", "audio_pll1_out", "video_pll1_out", "sys3_pll_out", };
>  
> @@ -411,6 +413,9 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MQ_CLK_GPU_CORE_DIV] = imx8m_clk_hw_composite_core("gpu_core_div", imx8mq_gpu_core_sels, base + 0x8180);
>  	hws[IMX8MQ_CLK_GPU_SHADER_DIV] = imx8m_clk_hw_composite("gpu_shader_div", imx8mq_gpu_shader_sels, base + 0x8200);
>  
> +	/* CORE SEL */
> +	hws[IMX8MQ_CLK_A53_CORE] = imx_clk_hw_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels), CLK_IS_CRITICAL);
> +
>  	/* BUS */
>  	hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mq_main_axi_sels, base + 0x8800);
>  	hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi", imx8mq_enet_axi_sels, base + 0x8880);
> @@ -574,11 +579,14 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MQ_GPT_3M_CLK] = imx_clk_hw_fixed_factor("gpt_3m", "osc_25m", 1, 8);
>  	hws[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
>  
> -	hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
> -					   hws[IMX8MQ_CLK_A53_DIV]->clk,
> -					   hws[IMX8MQ_CLK_A53_SRC]->clk,
> +	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_SRC], hws[IMX8MQ_SYS1_PLL_800M]);
> +	clk_hw_set_parent(hws[IMX8MQ_CLK_A53_CORE], hws[IMX8MQ_ARM_PLL_OUT]);
> +
> +	hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
> +					   hws[IMX8MQ_CLK_A53_CORE]->clk,
> +					   hws[IMX8MQ_CLK_A53_CORE]->clk,
>  					   hws[IMX8MQ_ARM_PLL_OUT]->clk,
> -					   hws[IMX8MQ_SYS1_PLL_800M]->clk);
> +					   hws[IMX8MQ_CLK_A53_DIV]->clk);
>  
>  	imx_check_clk_hws(hws, IMX8MQ_CLK_END);
>  
> diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
> index 3bab9b21c8d7..ac71e9e502b8 100644
> --- a/include/dt-bindings/clock/imx8mq-clock.h
> +++ b/include/dt-bindings/clock/imx8mq-clock.h
> @@ -424,6 +424,8 @@
>  #define IMX8MQ_SYS2_PLL_500M_CG			283
>  #define IMX8MQ_SYS2_PLL_1000M_CG		284
>  
> -#define IMX8MQ_CLK_END				285
> +#define IMX8MQ_CLK_A53_CORE			285
> +
> +#define IMX8MQ_CLK_END				286
>  
>  #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
> -- 
> 2.16.4
>