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From:   Stefan Asserhall <stefana@xilinx.com>
To:     Will Deacon <will@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>
CC:     Michal Simek <michals@xilinx.com>,
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        "arnd@arndb.de" <arnd@arndb.de>, Boqun Feng <boqun.feng@gmail.com>,
        "paulmck@kernel.org" <paulmck@kernel.org>
Subject: RE: [PATCH 7/7] microblaze: Do atomic operations by using exclusive
 ops
Thread-Topic: [PATCH 7/7] microblaze: Do atomic operations by using exclusive
 ops
Thread-Index: AQHV4bsTNSWG8PcZ4UGUKf7UEuD+JqgXthkAgAEPaACAAA6lgIAABQqAgAANMICAAAERUA==
Date:   Thu, 13 Feb 2020 10:14:13 +0000
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> On Thu, Feb 13, 2020 at 10:16:51AM +0100, Peter Zijlstra wrote:
> > On Thu, Feb 13, 2020 at 09:58:49AM +0100, Peter Zijlstra wrote:
> >
> > > The thing is, your bog standard LL/SC _SHOULD_ fail the SC if
> > > someone else does a regular store to the same variable. See the
> > > example in Documentation/atomic_t.txt.
> > >
> > > That is, a competing SW/SWI should result in the interconnect
> > > responding with something other than EXOKAY, the SWX should fail and
> MSR[C] <- 1.
> >
> > The thing is; we have code that relies on this behaviour. There are a
> > few crusty SMP archs that sorta-kinda limp along (mostly by disabling
> > some of the code and praying the rest doesn't trigger too often), but
> > we really should not allow more broken SMP archs.
>=20
> I did find this in the linked pdf:
>=20
>   | If the store [swx] is successful, the sequence of instructions from
>   | the semaphore load to the semaphore store appear to be executed
>   | atomically - no other device modified the semaphore location between
>   | the read and the update.
>=20
> which sounds like we're ok, although it could be better worded.
>=20
> One part I haven't figured out is what happens if you take an interrupt b=
etween
> the lwx and the swx and whether you can end up succeeding thanks to
> somebody else's reservation. Also, the manual is silent about the interac=
tion
> with TLB invalidation and just refers to "address" when talking about the
> reservation. What happens if a user thread triggers CoW while another is =
in the
> middle of a lwx/swx?
>=20
> Will

The manual says "Reset, interrupts, exceptions, and breaks (including the B=
RK=20
and BRKI instructions) all clear the reservation." In case of a TLB invalid=
ation=20
between lwx and swx, you will get a TLB miss exception when attempting the
swx, and the reservation will be cleared due to the exception.

Stefan