Received: by 2002:a25:1506:0:0:0:0:0 with SMTP id 6csp690562ybv; Thu, 13 Feb 2020 07:50:15 -0800 (PST) X-Google-Smtp-Source: APXvYqyF9SwDoeZibD186H60xy3hfZNaY/8vufDYq5ZPr/+WfD2V8paSK9JQzARBL8LMt/95N3Au X-Received: by 2002:a9d:7342:: with SMTP id l2mr13891300otk.98.1581609015579; Thu, 13 Feb 2020 07:50:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581609015; cv=none; d=google.com; s=arc-20160816; b=s166LUA8fPnIIU5Y82DMTXM1DAXSB6au82DkZsJDGQDhUozks5191ibb+YS4KcCk7a UiOEyySRQ1SHsPia+M/caPApHpPT8Oxs1UYx9GQ5Ur9d68H427diSv2DMEGQuLtzRSl0 Y+8hmHwdMesCvpH+liWJunm1z9hdJ8MoJtLJHfXviVUPmmvhhBmZ6ikjDJg77UQVb90M C21kmOmE71mDz4/NpLjyud16taydNcbJf5cmCru2OORskNQKooMhFgmntLU3COchxGWY vR1CGK5MNBDYq6RZRjNWhbTue+a8tngPHunBNOgZuZB1f34EGMZIoLpW2lmmqSUyDrIK 1Nzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=maN0QTQlGgmosYW48QJh/OOohIhJsfrryLRKbH1aGvE=; b=tT+5kruPehTTo9o+qKP6E3dhV56+yRlmIL668KgyoagIlTbONBfV2rf+LcJzguCzMZ kN32x2P7EGm3l6wqMO/IllOCsacuoPo74MZm5K0tZbwqa6FPCQtY/ZrgCMP2kyX9R24G M/mMGR0EmqNQsuf96vjYFf2lhrTpmEVaImvmuLKoAGooVDQqc7mIo6OwFfoPb0x1JiHF WbhbxwI5dFuZnYrfjKo10yq+b+KoL1IteeOiFdmtfA4/NbFwd6c3uZXNqwS27rkdlIKs 64hUmNh8wtjHD+LJa2C78RnfwnB3jUZGTYWSkXyUOw+tmLU6Sp6XztPyHHsSak7YeOo/ 1nYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=fH21bh7x; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h18si1273935otj.114.2020.02.13.07.50.02; Thu, 13 Feb 2020 07:50:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=fH21bh7x; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387963AbgBMPt7 (ORCPT + 99 others); Thu, 13 Feb 2020 10:49:59 -0500 Received: from mail.kernel.org ([198.145.29.99]:45638 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387597AbgBMP0e (ORCPT ); Thu, 13 Feb 2020 10:26:34 -0500 Received: from localhost (unknown [104.132.1.104]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4FAED24671; Thu, 13 Feb 2020 15:26:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1581607593; bh=JiGW1ZKtwS4BdyGbnx+B4dmbqP/SL5amfLB4HyxTAn4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fH21bh7xp94fgrsF8uBzstK9A2ZgUY+6SszB1sQqeddTz2sLi3i1RH15bxKFjs9yR 6lm4KP8ifmcvAsNyEbQCXgDRSYSpxLY4ojLQpG/s0I9WE4TR421W6l6j+d63xXQMID PLtEbvNk1SwBj6rOM+/g2i/Y0jucs+OFt7qKYbGY= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Tero Kristo , Benoit Parrot , Tony Lindgren Subject: [PATCH 4.19 25/52] ARM: dts: am43xx: add support for clkout1 clock Date: Thu, 13 Feb 2020 07:21:06 -0800 Message-Id: <20200213151820.578001517@linuxfoundation.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200213151810.331796857@linuxfoundation.org> References: <20200213151810.331796857@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tero Kristo commit 01053dadb79d63b65f7b353e68b4b6ccf4effedb upstream. clkout1 clock node and its generation tree was missing. Add this based on the data on TRM and PRCM functional spec. commit 664ae1ab2536 ("ARM: dts: am43xx: add clkctrl nodes") effectively reverted this commit 8010f13a40d3 ("ARM: dts: am43xx: add support for clkout1 clock") which is needed for the ov2659 camera sensor clock definition hence it is being re-applied here. Note that because of the current dts node name dependency for mapping to clock domain, we must still use "clkout1-*ck" naming instead of generic "clock@" naming for the node. And because of this, it's probably best to apply the dts node addition together along with the other clock changes. Fixes: 664ae1ab2536 ("ARM: dts: am43xx: add clkctrl nodes") Signed-off-by: Tero Kristo Tested-by: Benoit Parrot Acked-by: Tony Lindgren Signed-off-by: Benoit Parrot Signed-off-by: Tony Lindgren Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/am43xx-clocks.dtsi | 54 +++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -707,6 +707,60 @@ ti,bit-shift = <8>; reg = <0x2a48>; }; + + clkout1_osc_div_ck: clkout1-osc-div-ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin_ck>; + ti,bit-shift = <20>; + ti,max-div = <4>; + reg = <0x4100>; + }; + + clkout1_src2_mux_ck: clkout1-src2-mux-ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, + <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, + <&dpll_mpu_m2_ck>; + reg = <0x4100>; + }; + + clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout1_src2_mux_ck>; + ti,bit-shift = <4>; + ti,max-div = <8>; + reg = <0x4100>; + }; + + clkout1_src2_post_div_ck: clkout1-src2-post-div-ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout1_src2_pre_div_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-power-of-two; + reg = <0x4100>; + }; + + clkout1_mux_ck: clkout1-mux-ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, + <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; + ti,bit-shift = <16>; + reg = <0x4100>; + }; + + clkout1_ck: clkout1-ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkout1_mux_ck>; + ti,bit-shift = <23>; + reg = <0x4100>; + }; }; &prcm {